IB/mlx4: Add strong ordering to local inval and fast reg work requests (2ac6bf4d) · Commits · 戴 / test

The ConnectX Programmer's Reference Manual states that the "SO" bit must be set when posting Fast Register and Local Invalidate send work requests. When this bit is set, the work request will be executed only after all previous work requests on the send queue have been executed. (If the bit is not set, Fast Register and Local Invalidate WQEs may begin execution too early, which violates the defined semantics for these operations) This fixes the issue with NFS/RDMA reported in <http://lists.openfabrics.org/pipermail/general/2009-April/059253.html > Signed-off-by:

Jack Morgenstein <jackm@dev.mellanox.co.il> Cc: <stable@kernel.org> Signed-off-by:

Roland Dreier <rolandd@cisco.com>

drivers/infiniband/hw/mlx4/qp.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -1585,12 +1585,16 @@ int mlx4_ib_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
		break;

		case IB_WR_LOCAL_INV:
		ctrl->srcrb_flags \|=
		cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
		set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
		wqe += sizeof (struct mlx4_wqe_local_inval_seg);
		size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
		break;

		case IB_WR_FAST_REG_MR:
		ctrl->srcrb_flags \|=
		cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
		set_fmr_seg(wqe, wr);
		wqe += sizeof (struct mlx4_wqe_fmr_seg);
		size += sizeof (struct mlx4_wqe_fmr_seg) / 16;

include/linux/mlx4/qp.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -165,6 +165,7 @@ enum {
		MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
		MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
		MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
		MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
		};

		struct mlx4_wqe_ctrl_seg {

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