Commit 2aad2bf8 authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs: add gaudi asic registers header files 



Add the relevant GAUDI ASIC registers header files. These files are
generated automatically from a tool maintained by the VLSI engineers.

There are more files which are not upstreamed because only very few defines
from those files are used in the driver. For those files, we copied the
relevant defines into gaudi_regs.h and gaudi_masks.h, to reduce the size of
this patch.

Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent fca72fbb

drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h

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/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright 2016-2018 HabanaLabs, Ltd.

 * All Rights Reserved.

 *

 */



/************************************

 ** This is an auto-generated file **

 **       DO NOT EDIT BELOW        **

 ************************************/



#ifndef ASIC_REG_CPU_IF_REGS_H_

#define ASIC_REG_CPU_IF_REGS_H_



/*

 *****************************************

 *   CPU_IF (Prototype: CPU_IF)

 *****************************************

 */



#define mmCPU_IF_ARUSER_OVR                                          0x442104



#define mmCPU_IF_ARUSER_OVR_EN                                       0x442108



#define mmCPU_IF_AWUSER_OVR                                          0x44210C



#define mmCPU_IF_AWUSER_OVR_EN                                       0x442110



#define mmCPU_IF_AXCACHE_OVR                                         0x442114



#define mmCPU_IF_LOCK_OVR                                            0x442118



#define mmCPU_IF_PROT_OVR                                            0x44211C



#define mmCPU_IF_MAX_OUTSTANDING                                     0x442120



#define mmCPU_IF_EARLY_BRESP_EN                                      0x442124



#define mmCPU_IF_FORCE_RSP_OK                                        0x442128



#define mmCPU_IF_CPU_MSB_ADDR                                        0x44212C



#define mmCPU_IF_AXI_SPLIT_INTR                                      0x442130



#define mmCPU_IF_TOTAL_WR_CNT                                        0x442140



#define mmCPU_IF_INFLIGHT_WR_CNT                                     0x442144



#define mmCPU_IF_TOTAL_RD_CNT                                        0x442150



#define mmCPU_IF_INFLIGHT_RD_CNT                                     0x442154



#define mmCPU_IF_PF_PQ_PI                                            0x442200



#define mmCPU_IF_PQ_BASE_ADDR_LOW                                    0x442204



#define mmCPU_IF_PQ_BASE_ADDR_HIGH                                   0x442208



#define mmCPU_IF_PQ_LENGTH                                           0x44220C



#define mmCPU_IF_CQ_BASE_ADDR_LOW                                    0x442210



#define mmCPU_IF_CQ_BASE_ADDR_HIGH                                   0x442214



#define mmCPU_IF_CQ_LENGTH                                           0x442218



#define mmCPU_IF_EQ_BASE_ADDR_LOW                                    0x442220



#define mmCPU_IF_EQ_BASE_ADDR_HIGH                                   0x442224



#define mmCPU_IF_EQ_LENGTH                                           0x442228



#define mmCPU_IF_EQ_RD_OFFS                                          0x44222C



#define mmCPU_IF_QUEUE_INIT                                          0x442230



#define mmCPU_IF_TPC_SERR_INTR_STS                                   0x442300



#define mmCPU_IF_TPC_SERR_INTR_CLR                                   0x442304



#define mmCPU_IF_TPC_SERR_INTR_MASK                                  0x442308



#define mmCPU_IF_TPC_DERR_INTR_STS                                   0x442310



#define mmCPU_IF_TPC_DERR_INTR_CLR                                   0x442314



#define mmCPU_IF_TPC_DERR_INTR_MASK                                  0x442318



#define mmCPU_IF_DMA_SERR_INTR_STS                                   0x442320



#define mmCPU_IF_DMA_SERR_INTR_CLR                                   0x442324



#define mmCPU_IF_DMA_SERR_INTR_MASK                                  0x442328



#define mmCPU_IF_DMA_DERR_INTR_STS                                   0x442330



#define mmCPU_IF_DMA_DERR_INTR_CLR                                   0x442334



#define mmCPU_IF_DMA_DERR_INTR_MASK                                  0x442338



#define mmCPU_IF_SRAM_SERR_INTR_STS                                  0x442340



#define mmCPU_IF_SRAM_SERR_INTR_CLR                                  0x442344



#define mmCPU_IF_SRAM_SERR_INTR_MASK                                 0x442348



#define mmCPU_IF_SRAM_DERR_INTR_STS                                  0x442350



#define mmCPU_IF_SRAM_DERR_INTR_CLR                                  0x442354



#define mmCPU_IF_SRAM_DERR_INTR_MASK                                 0x442358



#define mmCPU_IF_NIC_SERR_INTR_STS                                   0x442360



#define mmCPU_IF_NIC_SERR_INTR_CLR                                   0x442364



#define mmCPU_IF_NIC_SERR_INTR_MASK                                  0x442368



#define mmCPU_IF_NIC_DERR_INTR_STS                                   0x442370



#define mmCPU_IF_NIC_DERR_INTR_CLR                                   0x442374



#define mmCPU_IF_NIC_DERR_INTR_MASK                                  0x442378



#define mmCPU_IF_DMA_IF_SERR_INTR_STS                                0x442380



#define mmCPU_IF_DMA_IF_SERR_INTR_CLR                                0x442384



#define mmCPU_IF_DMA_IF_SERR_INTR_MASK                               0x442388



#define mmCPU_IF_DMA_IF_DERR_INTR_STS                                0x442390



#define mmCPU_IF_DMA_IF_DERR_INTR_CLR                                0x442394



#define mmCPU_IF_DMA_IF_DERR_INTR_MASK                               0x442398



#define mmCPU_IF_HBM_SERR_INTR_STS                                   0x4423A0



#define mmCPU_IF_HBM_SERR_INTR_CLR                                   0x4423A4



#define mmCPU_IF_HBM_SERR_INTR_MASK                                  0x4423A8



#define mmCPU_IF_HBM_DERR_INTR_STS                                   0x4423B0



#define mmCPU_IF_HBM_DERR_INTR_CLR                                   0x4423B4



#define mmCPU_IF_HBM_DERR_INTR_MASK                                  0x4423B8



#define mmCPU_IF_PLL_SEI_INTR_STS                                    0x442400



#define mmCPU_IF_PLL_SEI_INTR_CLR                                    0x442404



#define mmCPU_IF_PLL_SEI_INTR_MASK                                   0x442408



#define mmCPU_IF_NIC_SEI_INTR_STS                                    0x442410



#define mmCPU_IF_NIC_SEI_INTR_CLR                                    0x442414



#define mmCPU_IF_NIC_SEI_INTR_MASK                                   0x442418



#define mmCPU_IF_DMA_SEI_INTR_STS                                    0x442420



#define mmCPU_IF_DMA_SEI_INTR_CLR                                    0x442424



#define mmCPU_IF_DMA_SEI_INTR_MASK                                   0x442428



#define mmCPU_IF_DMA_IF_SEI_INTR_STS                                 0x442430



#define mmCPU_IF_DMA_IF_SEI_INTR_CLR                                 0x442434



#define mmCPU_IF_DMA_IF_SEI_INTR_MASK                                0x442438



#endif /* ASIC_REG_CPU_IF_REGS_H_ */

drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h

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/* SPDX-License-Identifier: GPL-2.0

 *

 * Copyright 2016-2018 HabanaLabs, Ltd.

 * All Rights Reserved.

 *

 */



/************************************

 ** This is an auto-generated file **

 **       DO NOT EDIT BELOW        **

 ************************************/



#ifndef ASIC_REG_DMA0_CORE_MASKS_H_

#define ASIC_REG_DMA0_CORE_MASKS_H_



/*

 *****************************************

 *   DMA0_CORE (Prototype: DMA_CORE)

 *****************************************

 */



/* DMA0_CORE_CFG_0 */

#define DMA0_CORE_CFG_0_EN_SHIFT                                     0

#define DMA0_CORE_CFG_0_EN_MASK                                      0x1



/* DMA0_CORE_CFG_1 */

#define DMA0_CORE_CFG_1_HALT_SHIFT                                   0

#define DMA0_CORE_CFG_1_HALT_MASK                                    0x1

#define DMA0_CORE_CFG_1_FLUSH_SHIFT                                  1

#define DMA0_CORE_CFG_1_FLUSH_MASK                                   0x2

#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT                          2

#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK                           0x4



/* DMA0_CORE_LBW_MAX_OUTSTAND */

#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT                         0

#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK                          0x1F



/* DMA0_CORE_SRC_BASE_LO */

#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT                              0

#define DMA0_CORE_SRC_BASE_LO_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_SRC_BASE_HI */

#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT                              0

#define DMA0_CORE_SRC_BASE_HI_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_BASE_LO */

#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT                              0

#define DMA0_CORE_DST_BASE_LO_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_BASE_HI */

#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT                              0

#define DMA0_CORE_DST_BASE_HI_VAL_MASK                               0xFFFFFF

#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT                        24

#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK                         0xFF000000



/* DMA0_CORE_SRC_TSIZE_1 */

#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT                              0

#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_SRC_STRIDE_1 */

#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT                             0

#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_SRC_TSIZE_2 */

#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT                              0

#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_SRC_STRIDE_2 */

#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT                             0

#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_SRC_TSIZE_3 */

#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT                              0

#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_SRC_STRIDE_3 */

#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT                             0

#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_SRC_TSIZE_4 */

#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT                              0

#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_SRC_STRIDE_4 */

#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT                             0

#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_SRC_TSIZE_0 */

#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT                              0

#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_TSIZE_1 */

#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT                              0

#define DMA0_CORE_DST_TSIZE_1_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_STRIDE_1 */

#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT                             0

#define DMA0_CORE_DST_STRIDE_1_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_DST_TSIZE_2 */

#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT                              0

#define DMA0_CORE_DST_TSIZE_2_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_STRIDE_2 */

#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT                             0

#define DMA0_CORE_DST_STRIDE_2_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_DST_TSIZE_3 */

#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT                              0

#define DMA0_CORE_DST_TSIZE_3_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_STRIDE_3 */

#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT                             0

#define DMA0_CORE_DST_STRIDE_3_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_DST_TSIZE_4 */

#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT                              0

#define DMA0_CORE_DST_TSIZE_4_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_DST_STRIDE_4 */

#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT                             0

#define DMA0_CORE_DST_STRIDE_4_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_DST_TSIZE_0 */

#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT                              0

#define DMA0_CORE_DST_TSIZE_0_VAL_MASK                               0xFFFFFFFF



/* DMA0_CORE_COMMIT */

#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT                            0

#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK                             0x1

#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT                             1

#define DMA0_CORE_COMMIT_TRANSPOSE_MASK                              0x2

#define DMA0_CORE_COMMIT_DTYPE_SHIFT                                 2

#define DMA0_CORE_COMMIT_DTYPE_MASK                                  0x4

#define DMA0_CORE_COMMIT_LIN_SHIFT                                   3

#define DMA0_CORE_COMMIT_LIN_MASK                                    0x8

#define DMA0_CORE_COMMIT_MEM_SET_SHIFT                               4

#define DMA0_CORE_COMMIT_MEM_SET_MASK                                0x10

#define DMA0_CORE_COMMIT_COMPRESS_SHIFT                              5

#define DMA0_CORE_COMMIT_COMPRESS_MASK                               0x20

#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT                            6

#define DMA0_CORE_COMMIT_DECOMPRESS_MASK                             0x40

#define DMA0_CORE_COMMIT_CTX_ID_SHIFT                                16

#define DMA0_CORE_COMMIT_CTX_ID_MASK                                 0xFF0000



/* DMA0_CORE_WR_COMP_WDATA */

#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT                            0

#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK                             0xFFFFFFFF



/* DMA0_CORE_WR_COMP_ADDR_LO */

#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT                          0

#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK                           0xFFFFFFFF



/* DMA0_CORE_WR_COMP_ADDR_HI */

#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT                          0

#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK                           0xFFFFFFFF



/* DMA0_CORE_WR_COMP_AWUSER_31_11 */

#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT                     0

#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK                      0x1FFFFF



/* DMA0_CORE_TE_NUMROWS */

#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT                               0

#define DMA0_CORE_TE_NUMROWS_VAL_MASK                                0xFFFFFFFF



/* DMA0_CORE_PROT */

#define DMA0_CORE_PROT_VAL_SHIFT                                     0

#define DMA0_CORE_PROT_VAL_MASK                                      0x1

#define DMA0_CORE_PROT_ERR_VAL_SHIFT                                 1

#define DMA0_CORE_PROT_ERR_VAL_MASK                                  0x2



/* DMA0_CORE_SECURE_PROPS */

#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT                            0

#define DMA0_CORE_SECURE_PROPS_ASID_MASK                             0x3FF

#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT                            10

#define DMA0_CORE_SECURE_PROPS_MMBP_MASK                             0x400



/* DMA0_CORE_NON_SECURE_PROPS */

#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT                        0

#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK                         0x3FF

#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT                        10

#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK                         0x400



/* DMA0_CORE_RD_MAX_OUTSTAND */

#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT                          0

#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK                           0xFFF



/* DMA0_CORE_RD_MAX_SIZE */

#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT                             0

#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK                              0x7FF

#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT                               16

#define DMA0_CORE_RD_MAX_SIZE_MD_MASK                                0x7FF0000



/* DMA0_CORE_RD_ARCACHE */

#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT                               0

#define DMA0_CORE_RD_ARCACHE_VAL_MASK                                0xF



/* DMA0_CORE_RD_ARUSER_31_11 */

#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT                          0

#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK                           0x1FFFFF



/* DMA0_CORE_RD_INFLIGHTS */

#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT                             0

#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_WR_MAX_OUTSTAND */

#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT                          0

#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK                           0xFFF



/* DMA0_CORE_WR_MAX_AWID */

#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT                              0

#define DMA0_CORE_WR_MAX_AWID_VAL_MASK                               0xFFFF



/* DMA0_CORE_WR_AWCACHE */

#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT                               0

#define DMA0_CORE_WR_AWCACHE_VAL_MASK                                0xF



/* DMA0_CORE_WR_AWUSER_31_11 */

#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT                          0

#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK                           0x1FFFFF



/* DMA0_CORE_WR_INFLIGHTS */

#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT                             0

#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK                              0xFFFF



/* DMA0_CORE_RD_RATE_LIM_CFG_0 */

#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                  0

#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                   0xFF

#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT                        16

#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK                         0xFF0000



/* DMA0_CORE_RD_RATE_LIM_CFG_1 */

#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT                       0

#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK                        0xFF

#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT                         31

#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK                          0x80000000



/* DMA0_CORE_WR_RATE_LIM_CFG_0 */

#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                  0

#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                   0xFF

#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT                        16

#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK                         0xFF0000



/* DMA0_CORE_WR_RATE_LIM_CFG_1 */

#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT                       0

#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK                        0xFF

#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT                         31

#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK                          0x80000000



/* DMA0_CORE_ERR_CFG */

#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT                           0

#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK                            0x1

#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT                          1

#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK                           0x2



/* DMA0_CORE_ERR_CAUSE */

#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT                         0

#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK                          0x1

#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT                         1

#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK                          0x2

#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT                         2

#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK                          0x4

#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT                           3

#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK                            0x8



/* DMA0_CORE_ERRMSG_ADDR_LO */

#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT                           0

#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK                            0xFFFFFFFF



/* DMA0_CORE_ERRMSG_ADDR_HI */

#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT                           0

#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK                            0xFFFFFFFF



/* DMA0_CORE_ERRMSG_WDATA */

#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT                             0

#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK                              0xFFFFFFFF



/* DMA0_CORE_STS0 */

#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT                              0

#define DMA0_CORE_STS0_RD_REQ_CNT_MASK                               0x7FFF

#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT                              16

#define DMA0_CORE_STS0_WR_REQ_CNT_MASK                               0x7FFF0000

#define DMA0_CORE_STS0_BUSY_SHIFT                                    31

#define DMA0_CORE_STS0_BUSY_MASK                                     0x80000000



/* DMA0_CORE_STS1 */

#define DMA0_CORE_STS1_IS_HALT_SHIFT                                 0

#define DMA0_CORE_STS1_IS_HALT_MASK                                  0x1



/* DMA0_CORE_RD_DBGMEM_ADD */

#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT                            0

#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK                             0xFFFFFFFF



/* DMA0_CORE_RD_DBGMEM_DATA_WR */

#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT                        0

#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK                         0xFFFFFFFF



/* DMA0_CORE_RD_DBGMEM_DATA_RD */

#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT                        0

#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK                         0xFFFFFFFF



/* DMA0_CORE_RD_DBGMEM_CTRL */

#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT                        0

#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK                         0x1



/* DMA0_CORE_RD_DBGMEM_RC */

#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT                           0

#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK                            0x1



/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */



/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */



/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */



/* DMA0_CORE_DBG_DESC_CNT */

#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT                  0

#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK                   0xFFFFFFFF



/* DMA0_CORE_DBG_STS */

#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT                          0

#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK                           0x1

#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT                          1

#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK                           0x2

#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT                         2

#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK                          0x4

#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT                         3

#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK                          0x8

#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT                         4

#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK                          0x10

#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT                        5

#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK                         0x20

#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT                             6

#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK                              0x40

#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT                              7

#define DMA0_CORE_DBG_STS_TE_BUSY_MASK                               0x80

#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT                           8

#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK                            0x100

#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT                            9

#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK                             0x200

#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT                       20

#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK                        0x7FF00000



/* DMA0_CORE_DBG_RD_DESC_ID */



/* DMA0_CORE_DBG_WR_DESC_ID */



#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */

drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h

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drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h

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drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h

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