Merge tag 'socfpga-clk-fix-for-3.15' of... (2aa6dd07) · Commits · 戴 / test

drivers/clk/socfpga/clk-pll.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@
		#include <linux/clk-provider.h>
		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/of_address.h>

		#include "clk.h"

		@@ -43,6 +44,8 @@

		#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)

		void __iomem *clk_mgr_base_addr;

		static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
		unsigned long parent_rate)
		{
		@@ -87,6 +90,7 @@ static __init struct clk __socfpga_pll_init(struct device_node node,
		const char *clk_name = node->name;
		const char *parent_name[SOCFPGA_MAX_PARENTS];
		struct clk_init_data init;
		struct device_node *clkmgr_np;
		int rc;
		int i = 0;

		@@ -96,6 +100,9 @@ static __init struct clk __socfpga_pll_init(struct device_node node,
		if (WARN_ON(!pll_clk))
		return NULL;

		clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
		clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
		BUG_ON(!clk_mgr_base_addr);
		pll_clk->hw.reg = clk_mgr_base_addr + reg;

		of_property_read_string(node, "clock-output-names", &clk_name);

+3 −20

Original line number	Diff line number	Diff line
		@@ -17,28 +17,11 @@
		* You should have received a copy of the GNU General Public License
		* along with this program. If not, see <http://www.gnu.org/licenses/>.
		*/
		#include <linux/clk.h>
		#include <linux/clkdev.h>
		#include <linux/clk-provider.h>
		#include <linux/io.h>
		#include <linux/of.h>
		#include <linux/of_address.h>

		#include "clk.h"

		void __iomem *clk_mgr_base_addr;

		static const struct of_device_id socfpga_child_clocks[] __initconst = {
		{ .compatible = "altr,socfpga-pll-clock", socfpga_pll_init, },
		{ .compatible = "altr,socfpga-perip-clk", socfpga_periph_init, },
		{ .compatible = "altr,socfpga-gate-clk", socfpga_gate_init, },
		{},
		};

		static void __init socfpga_clkmgr_init(struct device_node *node)
		{
		clk_mgr_base_addr = of_iomap(node, 0);
		of_clk_init(socfpga_child_clocks);
		}
		CLK_OF_DECLARE(socfpga_mgr, "altr,clk-mgr", socfpga_clkmgr_init);
		CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
		CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
		CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);