Commit 2a5bc6c4 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Will Deacon
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arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register 



ID_ISAR0[31..28] bits are RES0 in ARMv8, Reserved/UNK in ARMv7. Currently
these bits get exposed through generic_id_ftr32[] which is not desirable.
Hence define an explicit ftr_id_isar0[] array for ID_ISAR0 register where
those bits can be hidden.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-2-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent f73531f0

arch/arm64/include/asm/sysreg.h

+8 −0
Original line number Diff line number Diff line
@@ -766,6 +766,14 @@ 
#define ID_ISAR4_WITHSHIFTS_SHIFT	4

#define ID_ISAR4_UNPRIV_SHIFT		0



#define ID_ISAR0_DIVIDE_SHIFT		24

#define ID_ISAR0_DEBUG_SHIFT		20

#define ID_ISAR0_COPROC_SHIFT		16

#define ID_ISAR0_CMPBRANCH_SHIFT	12

#define ID_ISAR0_BITFIELD_SHIFT		8

#define ID_ISAR0_BITCOUNT_SHIFT		4

#define ID_ISAR0_SWAP_SHIFT		0



#define ID_ISAR5_RDM_SHIFT		24

#define ID_ISAR5_CRC32_SHIFT		16

#define ID_ISAR5_SHA2_SHIFT		12

arch/arm64/kernel/cpufeature.c

+12 −2
Original line number Diff line number Diff line
@@ -370,6 +370,16 @@ static const struct arm64_ftr_bits ftr_dczid[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar5[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
@@ -451,7 +461,7 @@ static const struct arm64_ftr_bits ftr_zcr[] = { 
 * Common ftr bits for a 32bit register with all hidden, strict

 * attributes, with 4bit feature fields and a default safe value of

 * 0. Covers the following 32bit registers:

 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]

 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]

 */

static const struct arm64_ftr_bits ftr_generic_32bits[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
@@ -497,7 +507,7 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),



	/* Op1 = 0, CRn = 0, CRm = 2 */

	ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),

	ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),

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