drm/i915/icl: Drop redundant gamma mode mask (2a3902bd) · Commits · 戴 / test

gamma mode mask was not considering the 30th and 31st bits. Due to this state readout was masking these bits, causing a mismatch and false warning, even though the registers were updated correctly. Dropped the gamma mode mask as it is redundant and ideally entire register content should be matching. This resolves the state mismatch warnings. Signed-off-by:

Uma Shankar <uma.shankar@intel.com> Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1550689519-6977-1-git-send-email-uma.shankar@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109624

drivers/gpu/drm/i915/i915_reg.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -7151,7 +7151,6 @@ enum {
		#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
		#define PRE_CSC_GAMMA_ENABLE (1 << 31)
		#define POST_CSC_GAMMA_ENABLE (1 << 30)
		#define GAMMA_MODE_MODE_MASK (3 << 0)
		#define GAMMA_MODE_MODE_8BIT (0 << 0)
		#define GAMMA_MODE_MODE_10BIT (1 << 0)
		#define GAMMA_MODE_MODE_12BIT (2 << 0)

drivers/gpu/drm/i915/intel_display.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -9897,8 +9897,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
		intel_get_pipe_src_size(crtc, pipe_config);
		intel_get_crtc_ycbcr_config(crtc, pipe_config);

		pipe_config->gamma_mode =
		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
		pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));

		if (INTEL_GEN(dev_priv) >= 9) {
		u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));

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