Commit 2a346706 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'mediatek-drm-2016-06-20' of git://git.pengutronix.de/git/pza/linux into drm-next 

MT8173 HDMI support

- device tree binding documentation for MT8173 HDMI encoder, CEC, DDC,
  and PHY
- drivers for MT8173 HDMI encoder, CEC (HPD only for now), DDC, and PHY
- enable HDMI output via a custom SMCCC call
- add ddc-i2c-bus property to HDMI connector device tree binding

* tag 'mediatek-drm-2016-06-20' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
  drm/mediatek: enable hdmi output control bit
  drm/mediatek: Add HDMI support
  dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
parents 6559436d 9a449e0d

Documentation/devicetree/bindings/display/connector/hdmi-connector.txt

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@@ -8,6 +8,7 @@ Required properties: 
Optional properties:

- label: a symbolic name for the connector

- hpd-gpios: HPD GPIO number

- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing



Required nodes:

- Video port for HDMI input

Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt

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Mediatek HDMI Encoder

=====================



The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from

its parallel input.



Required properties:

- compatible: Should be "mediatek,<chip>-hdmi".

- reg: Physical base address and length of the controller's registers

- interrupts: The interrupt signal from the function block.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- clock-names: must contain "pixel", "pll", "bclk", and "spdif".

- phys: phandle link to the HDMI PHY node.

  See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.

- phy-names: must contain "hdmi"

- mediatek,syscon-hdmi: phandle link and register offset to the system

  configuration registers. For mt8173 this must be offset 0x900 into the

  MMSYS_CONFIG region: <&mmsys 0x900>.

- ports: A node containing input and output port nodes with endpoint

  definitions as documented in Documentation/devicetree/bindings/graph.txt.

- port@0: The input port in the ports node should be connected to a DPI output

  port.

- port@1: The output port in the ports node should be connected to the input

  port of a connector node that contains a ddc-i2c-bus property, or to the

  input port of an attached bridge chip, such as a SlimPort transmitter.



HDMI CEC

========



The HDMI CEC controller handles hotplug detection and CEC communication.



Required properties:

- compatible: Should be "mediatek,<chip>-cec"

- reg: Physical base address and length of the controller's registers

- interrupts: The interrupt signal from the function block.

- clocks: device clock



HDMI DDC

========



The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.

The Mediatek's I2C controller is used to interface with I2C devices.



Required properties:

- compatible: Should be "mediatek,<chip>-hdmi-ddc"

- reg: Physical base address and length of the controller's registers

- clocks: device clock

- clock-names: Should be "ddc-i2c".



HDMI PHY

========



The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel

output and drives the HDMI pads.



Required properties:

- compatible: "mediatek,<chip>-hdmi-phy"

- reg: Physical base address and length of the module's registers

- clocks: PLL reference clock

- clock-names: must contain "pll_ref"

- clock-output-names: must be "hdmitx_dig_cts" on mt8173

- #phy-cells: must be <0>

- #clock-cells: must be <0>



Optional properties:

- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa

- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c



Example:



cec: cec@10013000 {

	compatible = "mediatek,mt8173-cec";

	reg = <0 0x10013000 0 0xbc>;

	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&infracfg CLK_INFRA_CEC>;

};



hdmi_phy: hdmi-phy@10209100 {

	compatible = "mediatek,mt8173-hdmi-phy";

	reg = <0 0x10209100 0 0x24>;

	clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;

	clock-names = "pll_ref";

	clock-output-names = "hdmitx_dig_cts";

	mediatek,ibias = <0xa>;

	mediatek,ibias_up = <0x1c>;

	#clock-cells = <0>;

	#phy-cells = <0>;

};



hdmi_ddc0: i2c@11012000 {

	compatible = "mediatek,mt8173-hdmi-ddc";

	reg = <0 0x11012000 0 0x1c>;

	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&pericfg CLK_PERI_I2C5>;

	clock-names = "ddc-i2c";

};



hdmi0: hdmi@14025000 {

	compatible = "mediatek,mt8173-hdmi";

	reg = <0 0x14025000 0 0x400>;

	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&mmsys CLK_MM_HDMI_PIXEL>,

		 <&mmsys CLK_MM_HDMI_PLLCK>,

		 <&mmsys CLK_MM_HDMI_AUDIO>,

		 <&mmsys CLK_MM_HDMI_SPDIF>;

	clock-names = "pixel", "pll", "bclk", "spdif";

	pinctrl-names = "default";

	pinctrl-0 = <&hdmi_pin>;

	phys = <&hdmi_phy>;

	phy-names = "hdmi";

	mediatek,syscon-hdmi = <&mmsys 0x900>;

	assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;

	assigned-clock-parents = <&hdmi_phy>;



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;



			hdmi0_in: endpoint {

				remote-endpoint = <&dpi0_out>;

			};

		};



		port@1 {

			reg = <1>;



			hdmi0_out: endpoint {

				remote-endpoint = <&hdmi_con_in>;

			};

		};

	};

};



connector {

	compatible = "hdmi-connector";

	type = "a";

	ddc-i2c-bus = <&hdmiddc0>;



	port {

		hdmi_con_in: endpoint {

			remote-endpoint = <&hdmi0_out>;

		};

	};

};

drivers/gpu/drm/mediatek/Kconfig

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@@ -13,3 +13,11 @@ config DRM_MEDIATEK 
	  The module will be called mediatek-drm

	  This driver provides kernel mode setting and

	  buffer management to userspace.



config DRM_MEDIATEK_HDMI

	tristate "DRM HDMI Support for Mediatek SoCs"

	depends on DRM_MEDIATEK

	select SND_SOC_HDMI_CODEC if SND_SOC

	select GENERIC_PHY

	help

	  DRM/KMS HDMI driver for Mediatek SoCs

drivers/gpu/drm/mediatek/Makefile

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@@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \ 
		  mtk_dpi.o



obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o



mediatek-drm-hdmi-objs := mtk_cec.o \

			  mtk_hdmi.o \

			  mtk_hdmi_ddc.o \

			  mtk_mt8173_hdmi_phy.o



obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o

drivers/gpu/drm/mediatek/mtk_cec.c

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/*

 * Copyright (c) 2014 MediaTek Inc.

 * Author: Jie Qiu <jie.qiu@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>



#include "mtk_cec.h"



#define TR_CONFIG		0x00

#define CLEAR_CEC_IRQ			BIT(15)



#define CEC_CKGEN		0x04

#define CEC_32K_PDN			BIT(19)

#define PDN				BIT(16)



#define RX_EVENT		0x54

#define HDMI_PORD			BIT(25)

#define HDMI_HTPLG			BIT(24)

#define HDMI_PORD_INT_EN		BIT(9)

#define HDMI_HTPLG_INT_EN		BIT(8)



#define RX_GEN_WD		0x58

#define HDMI_PORD_INT_32K_STATUS	BIT(26)

#define RX_RISC_INT_32K_STATUS		BIT(25)

#define HDMI_HTPLG_INT_32K_STATUS	BIT(24)

#define HDMI_PORD_INT_32K_CLR		BIT(18)

#define RX_INT_32K_CLR			BIT(17)

#define HDMI_HTPLG_INT_32K_CLR		BIT(16)

#define HDMI_PORD_INT_32K_STA_MASK	BIT(10)

#define RX_RISC_INT_32K_STA_MASK	BIT(9)

#define HDMI_HTPLG_INT_32K_STA_MASK	BIT(8)

#define HDMI_PORD_INT_32K_EN		BIT(2)

#define RX_INT_32K_EN			BIT(1)

#define HDMI_HTPLG_INT_32K_EN		BIT(0)



#define NORMAL_INT_CTRL		0x5C

#define HDMI_HTPLG_INT_STA		BIT(0)

#define HDMI_PORD_INT_STA		BIT(1)

#define HDMI_HTPLG_INT_CLR		BIT(16)

#define HDMI_PORD_INT_CLR		BIT(17)

#define HDMI_FULL_INT_CLR		BIT(20)



struct mtk_cec {

	void __iomem *regs;

	struct clk *clk;

	int irq;

	bool hpd;

	void (*hpd_event)(bool hpd, struct device *dev);

	struct device *hdmi_dev;

	spinlock_t lock;

};



static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,

			       unsigned int bits)

{

	void __iomem *reg = cec->regs + offset;

	u32 tmp;



	tmp = readl(reg);

	tmp &= ~bits;

	writel(tmp, reg);

}



static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,

			     unsigned int bits)

{

	void __iomem *reg = cec->regs + offset;

	u32 tmp;



	tmp = readl(reg);

	tmp |= bits;

	writel(tmp, reg);

}



static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,

			 unsigned int val, unsigned int mask)

{

	u32 tmp = readl(cec->regs + offset) & ~mask;



	tmp |= val & mask;

	writel(val, cec->regs + offset);

}



void mtk_cec_set_hpd_event(struct device *dev,

			   void (*hpd_event)(bool hpd, struct device *dev),

			   struct device *hdmi_dev)

{

	struct mtk_cec *cec = dev_get_drvdata(dev);

	unsigned long flags;



	spin_lock_irqsave(&cec->lock, flags);

	cec->hdmi_dev = hdmi_dev;

	cec->hpd_event = hpd_event;

	spin_unlock_irqrestore(&cec->lock, flags);

}



bool mtk_cec_hpd_high(struct device *dev)

{

	struct mtk_cec *cec = dev_get_drvdata(dev);

	unsigned int status;



	status = readl(cec->regs + RX_EVENT);



	return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);

}



static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)

{

	mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);

	mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |

			 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);

	mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |

		     HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |

		     RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);

}



static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)

{

	mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);

}



static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)

{

	mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);

}



static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)

{

	mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);

	mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |

			 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);

	mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |

			 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);

	usleep_range(5, 10);

	mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |

			   HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);

	mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);

	mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |

			   RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);

}



static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)

{

	void (*hpd_event)(bool hpd, struct device *dev);

	struct device *hdmi_dev;

	unsigned long flags;



	spin_lock_irqsave(&cec->lock, flags);

	hpd_event = cec->hpd_event;

	hdmi_dev = cec->hdmi_dev;

	spin_unlock_irqrestore(&cec->lock, flags);



	if (hpd_event)

		hpd_event(hpd, hdmi_dev);

}



static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)

{

	struct device *dev = arg;

	struct mtk_cec *cec = dev_get_drvdata(dev);

	bool hpd;



	mtk_cec_clear_htplg_irq(cec);

	hpd = mtk_cec_hpd_high(dev);



	if (cec->hpd != hpd) {

		dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",

			cec->hpd, hpd);

		cec->hpd = hpd;

		mtk_cec_hpd_event(cec, hpd);

	}

	return IRQ_HANDLED;

}



static int mtk_cec_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct mtk_cec *cec;

	struct resource *res;

	int ret;



	cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);

	if (!cec)

		return -ENOMEM;



	platform_set_drvdata(pdev, cec);

	spin_lock_init(&cec->lock);



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	cec->regs = devm_ioremap_resource(dev, res);

	if (IS_ERR(cec->regs)) {

		ret = PTR_ERR(cec->regs);

		dev_err(dev, "Failed to ioremap cec: %d\n", ret);

		return ret;

	}



	cec->clk = devm_clk_get(dev, NULL);

	if (IS_ERR(cec->clk)) {

		ret = PTR_ERR(cec->clk);

		dev_err(dev, "Failed to get cec clock: %d\n", ret);

		return ret;

	}



	cec->irq = platform_get_irq(pdev, 0);

	if (cec->irq < 0) {

		dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);

		return cec->irq;

	}



	ret = devm_request_threaded_irq(dev, cec->irq, NULL,

					mtk_cec_htplg_isr_thread,

					IRQF_SHARED | IRQF_TRIGGER_LOW |

					IRQF_ONESHOT, "hdmi hpd", dev);

	if (ret) {

		dev_err(dev, "Failed to register cec irq: %d\n", ret);

		return ret;

	}



	ret = clk_prepare_enable(cec->clk);

	if (ret) {

		dev_err(dev, "Failed to enable cec clock: %d\n", ret);

		return ret;

	}



	mtk_cec_htplg_irq_init(cec);

	mtk_cec_htplg_irq_enable(cec);



	return 0;

}



static int mtk_cec_remove(struct platform_device *pdev)

{

	struct mtk_cec *cec = platform_get_drvdata(pdev);



	mtk_cec_htplg_irq_disable(cec);

	clk_disable_unprepare(cec->clk);

	return 0;

}



static const struct of_device_id mtk_cec_of_ids[] = {

	{ .compatible = "mediatek,mt8173-cec", },

	{}

};



struct platform_driver mtk_cec_driver = {

	.probe = mtk_cec_probe,

	.remove = mtk_cec_remove,

	.driver = {

		.name = "mediatek-cec",

		.of_match_table = mtk_cec_of_ids,

	},

};

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