Commit 2a2e01e7 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
100GbE Intel Wired LAN Driver Updates 2020-05-31

This series contains updates to the ice driver only.

Brett modifies the driver to allow users to clear a VF's
administratively set MAC address on the PF.  Fixes the driver to
recognize an existing VLAN tag when DMAC/SMAC is enabled in a packet.
Fixes an issue, so that VF's are reset after any VF port VLAN
modifications are made on the PF.  Made sure the register QRXFLXP_CNTXT
is cleared before writing a new value to ensure the previous value is
not passed forward.  Updates the PF to allow the VF to request a reset
as soon as it has been initialized.  Fixes an issue to ensure when a VSI
is created, it uses the current coalesce value, not the default value.

Paul allows untrusted VF's to add 16 filters.

Dan increases the timeout needed after a PFR to allow ample time for
package download.

Chinh adjust the define value for the number of PHY speeds we currently
support.  Changes the driver to ignore EMODE error when configuring the
PHY.

Jesse fixes an issue which was preventing a user from configuring the
interface before bringing it up.

Henry fixes the logic for adding back perfect flows after flow director
filter does a deletion.

Bruce fixes line wrappings to make it more consistent.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 03eaeda7 b5e19a64

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+2 −1
Original line number Diff line number Diff line
@@ -974,7 +974,7 @@ struct ice_aqc_get_phy_caps { 
#define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)

#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)

#define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)

#define ICE_PHY_TYPE_HIGH_MAX_INDEX		19

#define ICE_PHY_TYPE_HIGH_MAX_INDEX		5



struct ice_aqc_get_phy_caps_data {

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
@@ -1826,6 +1826,7 @@ enum ice_aq_err { 
	ICE_AQ_RC_EINVAL	= 14, /* Invalid argument */

	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */

	ICE_AQ_RC_ENOSYS	= 17, /* Function not implemented */

	ICE_AQ_RC_EMODE		= 21, /* Op not allowed in current dev mode */

	ICE_AQ_RC_ENOSEC	= 24, /* Missing security manifest */

	ICE_AQ_RC_EBADSIG	= 25, /* Bad RSA signature */

	ICE_AQ_RC_ESVN		= 26, /* SVN number prohibits this package */

drivers/net/ethernet/intel/ice/ice_base.c

+11 −22
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 


#include <net/xdp_sock_drv.h>

#include "ice_base.h"

#include "ice_lib.h"

#include "ice_dcb_lib.h"



/**
@@ -288,7 +289,6 @@ int ice_setup_rx_ctx(struct ice_ring *ring) 
	u32 rxdid = ICE_RXDID_FLEX_NIC;

	struct ice_rlan_ctx rlan_ctx;

	struct ice_hw *hw;

	u32 regval;

	u16 pf_q;

	int err;
@@ -387,25 +387,14 @@ int ice_setup_rx_ctx(struct ice_ring *ring) 


	/* Enable Flexible Descriptors in the queue context which

	 * allows this driver to select a specific receive descriptor format

	 * increasing context priority to pick up profile ID; default is 0x01;

	 * setting to 0x03 to ensure profile is programming if prev context is

	 * of same priority

	 */

	regval = rd32(hw, QRXFLXP_CNTXT(pf_q));

	if (vsi->type != ICE_VSI_VF) {

		regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &

			QRXFLXP_CNTXT_RXDID_IDX_M;



		/* increasing context priority to pick up profile ID;

		 * default is 0x01; setting to 0x03 to ensure profile

		 * is programming if prev context is of same priority

		 */

		regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &

			QRXFLXP_CNTXT_RXDID_PRIO_M;



	} else {

		regval &= ~(QRXFLXP_CNTXT_RXDID_IDX_M |

			    QRXFLXP_CNTXT_RXDID_PRIO_M |

			    QRXFLXP_CNTXT_TS_M);

	}

	wr32(hw, QRXFLXP_CNTXT(pf_q), regval);

	if (vsi->type != ICE_VSI_VF)

		ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3);

	else

		ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3);



	/* Absolute queue number out of 2K needs to be passed */

	err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);

drivers/net/ethernet/intel/ice/ice_common.c

+12 −2
Original line number Diff line number Diff line
@@ -964,7 +964,12 @@ static enum ice_status ice_pf_reset(struct ice_hw *hw) 


	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));



	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {

	/* Wait for the PFR to complete. The wait time is the global config lock

	 * timeout plus the PFR timeout which will account for a possible reset

	 * that is occurring during a download package operation.

	 */

	for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +

	     ICE_PF_RESET_WAIT_COUNT; cnt++) {

		reg = rd32(hw, PFGEN_CTRL);

		if (!(reg & PFGEN_CTRL_PFSWR_M))

			break;
@@ -2227,6 +2232,7 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 
		   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)

{

	struct ice_aq_desc desc;

	enum ice_status status;



	if (!cfg)

		return ICE_ERR_PARAM;
@@ -2255,7 +2261,11 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 
	ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);

	ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);



	return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);

	status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);

	if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)

		status = 0;



	return status;

}



/**

drivers/net/ethernet/intel/ice/ice_controlq.c

+1 −2
Original line number Diff line number Diff line
@@ -769,8 +769,7 @@ enum ice_status ice_create_all_ctrlq(struct ice_hw *hw) 
 *

 * Destroys the send and receive queue locks for a given control queue.

 */

static void

ice_destroy_ctrlq_locks(struct ice_ctl_q_info *cq)

static void ice_destroy_ctrlq_locks(struct ice_ctl_q_info *cq)

{

	mutex_destroy(&cq->sq_lock);

	mutex_destroy(&cq->rq_lock);

drivers/net/ethernet/intel/ice/ice_dcb_lib.c

+10 −18
Original line number Diff line number Diff line
@@ -791,41 +791,33 @@ void ice_update_dcb_stats(struct ice_pf *pf) 
 * ice_tx_prepare_vlan_flags_dcb - prepare VLAN tagging for DCB

 * @tx_ring: ring to send buffer on

 * @first: pointer to struct ice_tx_buf

 *

 * This should not be called if the outer VLAN is software offloaded as the VLAN

 * tag will already be configured with the correct ID and priority bits

 */

int

void

ice_tx_prepare_vlan_flags_dcb(struct ice_ring *tx_ring,

			      struct ice_tx_buf *first)

{

	struct sk_buff *skb = first->skb;



	if (!test_bit(ICE_FLAG_DCB_ENA, tx_ring->vsi->back->flags))

		return 0;

		return;



	/* Insert 802.1p priority into VLAN header */

	if ((first->tx_flags & (ICE_TX_FLAGS_HW_VLAN | ICE_TX_FLAGS_SW_VLAN)) ||

	if ((first->tx_flags & ICE_TX_FLAGS_HW_VLAN) ||

	    skb->priority != TC_PRIO_CONTROL) {

		first->tx_flags &= ~ICE_TX_FLAGS_VLAN_PR_M;

		/* Mask the lower 3 bits to set the 802.1p priority */

		first->tx_flags |= (skb->priority & 0x7) <<

				   ICE_TX_FLAGS_VLAN_PR_S;

		if (first->tx_flags & ICE_TX_FLAGS_SW_VLAN) {

			struct vlan_ethhdr *vhdr;

			int rc;



			rc = skb_cow_head(skb, 0);

			if (rc < 0)

				return rc;

			vhdr = (struct vlan_ethhdr *)skb->data;

			vhdr->h_vlan_TCI = htons(first->tx_flags >>

						 ICE_TX_FLAGS_VLAN_S);

		} else {

		/* if this is not already set it means a VLAN 0 + priority needs

		 * to be offloaded

		 */

		first->tx_flags |= ICE_TX_FLAGS_HW_VLAN;

	}

}



	return 0;

}



/**

 * ice_dcb_process_lldp_set_mib_change - Process MIB change

 * @pf: ptr to ice_pf

CRA Git | Maintained and supported by SUSTech CRA and CCSE