platform/x86: intel_pmc_core: Include Reserved IP for LTR (2a13096a) · Commits · 戴 / test

Recently introduced commit "platform/x86: intel_pmc_core: Show Latency Tolerance info <51337cd94d18184601ac0fb4cf1a02b8bbabc3d7> skipped the LTR from a reserved IP. Though this doesn't cause any functional issue but it is needed for the consumers of "ltr_ignore" as the index printing for "ltr_show" is missing. For example, w/o this change, a user that wants to ignore LTR from ME would do something like echo 5 > ltr_ignore but the index for ME is 6. Printing a reserved IP helps to properly calculate LTR ignore offsets. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by:

Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by:

Andy Shevchenko <andriy.shevchenko@linux.intel.com>

drivers/platform/x86/intel_pmc_core.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -108,6 +108,7 @@ static const struct pmc_bit_map spt_ltr_show_map[] = {
		{"SATA", SPT_PMC_LTR_SATA},
		{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
		{"XHCI", SPT_PMC_LTR_XHCI},
		{"Reserved", SPT_PMC_LTR_RESERVED},
		{"ME", SPT_PMC_LTR_ME},
		/* EVA is Enterprise Value Add, doesn't really exist on PCH */
		{"EVA", SPT_PMC_LTR_EVA},
		@@ -276,6 +277,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
		{"SATA", CNP_PMC_LTR_SATA},
		{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
		{"XHCI", CNP_PMC_LTR_XHCI},
		{"Reserved", CNP_PMC_LTR_RESERVED},
		{"ME", CNP_PMC_LTR_ME},
		/* EVA is Enterprise Value Add, doesn't really exist on PCH */
		{"EVA", CNP_PMC_LTR_EVA},

drivers/platform/x86/intel_pmc_core.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,7 @@
		#define SPT_PMC_LTR_SATA 0x368
		#define SPT_PMC_LTR_GBE 0x36C
		#define SPT_PMC_LTR_XHCI 0x370
		#define SPT_PMC_LTR_RESERVED 0x374
		#define SPT_PMC_LTR_ME 0x378
		#define SPT_PMC_LTR_EVA 0x37C
		#define SPT_PMC_LTR_SPC 0x380
		@@ -156,6 +157,7 @@ enum ppfear_regs {
		#define CNP_PMC_LTR_SATA 0x1B68
		#define CNP_PMC_LTR_GBE 0x1B6C
		#define CNP_PMC_LTR_XHCI 0x1B70
		#define CNP_PMC_LTR_RESERVED 0x1B74
		#define CNP_PMC_LTR_ME 0x1B78
		#define CNP_PMC_LTR_EVA 0x1B7C
		#define CNP_PMC_LTR_SPC 0x1B80

Admin message