Commit 2a040f0d authored Apr 14, 2020 by Matt Roper

drm/i915/tgl: Initialize multicast register steering for workarounds



Even though the bspec is missing gen12 register details for the MCR
selector register (0xFDC), this is confirmed by hardware folks to be a
mistake; the register does exist and we do indeed need to steer
multicast register reads to an appropriate instance the same as we did
on gen11.

Note that despite the lack of documentation we were still using the MCR
selector to read INSTDONE and such in read_subslice_reg() too.

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200414211118.2787489-4-matthew.d.roper@intel.com


Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

parent 80210152

drivers/gpu/drm/i915/gt/intel_workarounds.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -943,6 +943,8 @@ icl_gt_workarounds_init(struct drm_i915_private i915, struct i915_wa_list wal)
		static void
		tgl_gt_workarounds_init(struct drm_i915_private i915, struct i915_wa_list wal)
		{
		wa_init_mcr(i915, wal);

		/* Wa_1409420604:tgl */
		if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
		wa_write_or(wal,

Admin message