Commit 29daf869 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Always fault when _PAGE_ACCESSED is not set 



The kernel expects pte_young() to work regardless of CONFIG_SWAP.

Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.

This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.

Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.

Fixes: d069cb43 ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d9 ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
parent 0540b0d2

arch/powerpc/kernel/head_8xx.S

+2 −12
Original line number Diff line number Diff line
@@ -202,9 +202,7 @@ SystemCall: 


InstructionTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS)

	mtspr	SPRN_SPRG_SCRATCH1, r11

#endif



	/* If we are faulting a kernel address, we have to use the

	 * kernel page tables.
@@ -238,11 +236,9 @@ InstructionTLBMiss: 
	rlwimi	r11, r10, 32 - 9, _PMD_PAGE_512K

	mtspr	SPRN_MI_TWC, r11

#endif

#ifdef CONFIG_SWAP

	rlwinm	r11, r10, 32-5, _PAGE_PRESENT

	rlwinm	r11, r10, 32-7, _PAGE_PRESENT

	and	r11, r11, r10

	rlwimi	r10, r11, 0, _PAGE_PRESENT

#endif

	/* The Linux PTE won't go exactly into the MMU TLB.

	 * Software indicator bits 20 and 23 must be clear.

	 * Software indicator bits 22, 24, 25, 26, and 27 must be
@@ -256,9 +252,7 @@ InstructionTLBMiss: 


	/* Restore registers */

0:	mfspr	r10, SPRN_SPRG_SCRATCH0

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS)

	mfspr	r11, SPRN_SPRG_SCRATCH1

#endif

	rfi

	patch_site	0b, patch__itlbmiss_exit_1
@@ -268,9 +262,7 @@ InstructionTLBMiss: 
	addi	r10, r10, 1

	stw	r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_SPRG_SCRATCH0

#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)

	mfspr	r11, SPRN_SPRG_SCRATCH1

#endif

	rfi

#endif
@@ -316,11 +308,9 @@ DataStoreTLBMiss: 
	 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));

	 * r10 = (r10 & ~PRESENT) | r11;

	 */

#ifdef CONFIG_SWAP

	rlwinm	r11, r10, 32-5, _PAGE_PRESENT

	rlwinm	r11, r10, 32-7, _PAGE_PRESENT

	and	r11, r11, r10

	rlwimi	r10, r11, 0, _PAGE_PRESENT

#endif

	/* The Linux PTE won't go exactly into the MMU TLB.

	 * Software indicator bits 24, 25, 26, and 27 must be

	 * set.  All other Linux PTE bits control the behavior

CRA Git | Maintained and supported by SUSTech CRA and CCSE