[XTENSA] Remove non-rt signal handling (29c4dfd9) · Commits · 戴 / test

arch/xtensa/kernel/asm-offsets.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -39,6 +39,7 @@ int main(void)
	DEFINE(PT_LEND, offsetof (struct pt_regs, lend));		DEFINE(PT_LEND, offsetof (struct pt_regs, lend));
	DEFINE(PT_LCOUNT, offsetof (struct pt_regs, lcount));		DEFINE(PT_LCOUNT, offsetof (struct pt_regs, lcount));
	DEFINE(PT_SAR, offsetof (struct pt_regs, sar));		DEFINE(PT_SAR, offsetof (struct pt_regs, sar));
			DEFINE(PT_ICOUNTLEVEL, offsetof (struct pt_regs, icountlevel));
	DEFINE(PT_SYSCALL, offsetof (struct pt_regs, syscall));		DEFINE(PT_SYSCALL, offsetof (struct pt_regs, syscall));
	DEFINE(PT_AREG, offsetof (struct pt_regs, areg[0]));		DEFINE(PT_AREG, offsetof (struct pt_regs, areg[0]));
	DEFINE(PT_AREG0, offsetof (struct pt_regs, areg[0]));		DEFINE(PT_AREG0, offsetof (struct pt_regs, areg[0]));

arch/xtensa/kernel/entry.S

+14 −22

Original line number	Original line	Diff line number	Diff line
	@@ -125,8 +125,9 @@ _user_exception:

	movi a2, 0		movi a2, 0
	rsr a3, SAR		rsr a3, SAR
	wsr a2, ICOUNTLEVEL		xsr a2, ICOUNTLEVEL
	s32i a3, a1, PT_SAR		s32i a3, a1, PT_SAR
			s32i a2, a1, PT_ICOUNTLEVEL

	/* Rotate ws so that the current windowbase is at bit0. */		/* Rotate ws so that the current windowbase is at bit0. */
	/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */		/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
	@@ -276,8 +277,9 @@ _kernel_exception:

	movi a2, 0		movi a2, 0
	rsr a3, SAR		rsr a3, SAR
	wsr a2, ICOUNTLEVEL		xsr a2, ICOUNTLEVEL
	s32i a3, a1, PT_SAR		s32i a3, a1, PT_SAR
			s32i a2, a1, PT_ICOUNTLEVEL

	/* Rotate ws so that the current windowbase is at bit0. */		/* Rotate ws so that the current windowbase is at bit0. */
	/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */		/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
	@@ -330,14 +332,16 @@ _kernel_exception:

	common_exception:		common_exception:

	/* Save EXCVADDR, DEBUGCAUSE, and PC, and clear LCOUNT */		/* Save some registers, disable loops and clear the syscall flag. */

	rsr a2, DEBUGCAUSE		rsr a2, DEBUGCAUSE
	rsr a3, EPC_1		rsr a3, EPC_1
	s32i a2, a1, PT_DEBUGCAUSE		s32i a2, a1, PT_DEBUGCAUSE
	s32i a3, a1, PT_PC		s32i a3, a1, PT_PC

			movi a2, -1
	rsr a3, EXCVADDR		rsr a3, EXCVADDR
			s32i a2, a1, PT_SYSCALL
	movi a2, 0		movi a2, 0
	s32i a3, a1, PT_EXCVADDR		s32i a3, a1, PT_EXCVADDR
	xsr a2, LCOUNT		xsr a2, LCOUNT
	@@ -450,27 +454,8 @@ common_exception_return:

	/* Restore the state of the task and return from the exception. */		/* Restore the state of the task and return from the exception. */


	/* If we are returning from a user exception, and the process
	* to run next has PT_SINGLESTEP set, we want to setup
	* ICOUNT and ICOUNTLEVEL to step one instruction.
	* PT_SINGLESTEP is set by sys_ptrace (ptrace.c)
	*/

	4: /* a2 holds GET_CURRENT(a2,a1) */		4: /* a2 holds GET_CURRENT(a2,a1) */

	l32i a3, a2, TI_TASK
	l32i a3, a3, TASK_PTRACE
	bbci.l a3, PT_SINGLESTEP_BIT, 1f # jump if single-step flag is not set

	movi a3, -2 # PT_SINGLESTEP flag is set,
	movi a4, 1 # icountlevel of 1 means it won't
	wsr a3, ICOUNT # start counting until after rfe
	wsr a4, ICOUNTLEVEL # so setup icount & icountlevel.
	isync

	1:

	#if XCHAL_EXTRA_SA_SIZE		#if XCHAL_EXTRA_SA_SIZE

	/* For user exceptions, restore the extra state from the user's TCB. */		/* For user exceptions, restore the extra state from the user's TCB. */
	@@ -665,6 +650,13 @@ common_exception_exit:
	wsr a3, LEND		wsr a3, LEND
	wsr a2, LCOUNT		wsr a2, LCOUNT

			/* We control single stepping through the ICOUNTLEVEL register. */

			l32i a2, a1, PT_ICOUNTLEVEL
			movi a3, -2
			wsr a2, ICOUNTLEVEL
			wsr a3, ICOUNT

	/* Check if it was double exception. */		/* Check if it was double exception. */

	l32i a0, a1, PT_DEPC		l32i a0, a1, PT_DEPC

arch/xtensa/kernel/signal.c

+319 −476

File changed.

Preview size limit exceeded, changes collapsed.

include/asm-xtensa/coprocessor.h

+6 −2

Original line number	Original line	Diff line number	Diff line
	@@ -64,6 +64,7 @@ typedef struct {
	# define COPROCESSOR_INFO_SIZE 8		# define COPROCESSOR_INFO_SIZE 8
	# endif		# endif
	#endif		#endif
			#endif /* XCHAL_HAVE_CP */


	#ifndef __ASSEMBLY__		#ifndef __ASSEMBLY__
	@@ -74,8 +75,11 @@ extern void save_coprocessor_registers(void*, int);
	# else		# else
	# define release_coprocessors(task)		# define release_coprocessors(task)
	# endif		# endif
	#endif

	#endif		typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
			__attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));

			#endif /* !__ASSEMBLY__ */


	#endif /* _XTENSA_COPROCESSOR_H */		#endif /* _XTENSA_COPROCESSOR_H */

include/asm-xtensa/elf.h

+1 −2

Original line number	Original line	Diff line number	Diff line
	@@ -13,7 +13,6 @@
	#ifndef _XTENSA_ELF_H		#ifndef _XTENSA_ELF_H
	#define _XTENSA_ELF_H		#define _XTENSA_ELF_H

	#include <asm/variant/core.h>
	#include <asm/ptrace.h>		#include <asm/ptrace.h>

	/* Xtensa processor ELF architecture-magic number */		/* Xtensa processor ELF architecture-magic number */
	@@ -49,7 +48,7 @@ typedef struct {
	elf_greg_t lcount;		elf_greg_t lcount;
	elf_greg_t sar;		elf_greg_t sar;
	elf_greg_t syscall;		elf_greg_t syscall;
	elf_greg_t ar[XCHAL_NUM_AREGS];		elf_greg_t ar[64];
	} xtensa_gregset_t;		} xtensa_gregset_t;

	#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))		#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))

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