Commit 29c37341 authored by Paul Cercueil's avatar Paul Cercueil Committed by Stephen Boyd
Browse files

clk: ingenic: Use to_clk_info() macro for all clocks 



The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same thing the macro does, in-line.

Move the to_clk_info() macro to the top of the file, remove the
hardcoded BUG_ON(), and use it everywhere it makes sense.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9123e3a7

drivers/clk/ingenic/cgu.c

+15 −39
Original line number Diff line number Diff line
@@ -21,6 +21,12 @@ 


#define MHZ (1000 * 1000)



static inline const struct ingenic_cgu_clk_info *

to_clk_info(struct ingenic_clk *clk)

{

	return &clk->cgu->clock_info[clk->idx];

}



/**

 * ingenic_cgu_gate_get() - get the value of clock gate register bit

 * @cgu: reference to the CGU whose registers should be read
@@ -71,14 +77,13 @@ static unsigned long 
ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	const struct ingenic_cgu_pll_info *pll_info;

	unsigned m, n, od_enc, od;

	bool bypass;

	u32 ctl;



	clk_info = &cgu->clock_info[ingenic_clk->idx];

	BUG_ON(clk_info->type != CGU_CLK_PLL);

	pll_info = &clk_info->pll;
@@ -144,18 +149,6 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, 
		n * od);

}



static inline const struct ingenic_cgu_clk_info *to_clk_info(

		struct ingenic_clk *ingenic_clk)

{

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;



	clk_info = &cgu->clock_info[ingenic_clk->idx];

	BUG_ON(clk_info->type != CGU_CLK_PLL);



	return clk_info;

}



static long

ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,

		       unsigned long *prate)
@@ -290,13 +283,11 @@ static const struct clk_ops ingenic_pll_ops = { 
static u8 ingenic_clk_get_parent(struct clk_hw *hw)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	u32 reg;

	u8 i, hw_idx, idx = 0;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_MUX) {

		reg = readl(cgu->base + clk_info->mux.reg);

		hw_idx = (reg >> clk_info->mux.shift) &
@@ -318,14 +309,12 @@ static u8 ingenic_clk_get_parent(struct clk_hw *hw) 
static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	unsigned long flags;

	u8 curr_idx, hw_idx, num_poss;

	u32 reg, mask;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_MUX) {

		/*

		 * Convert the parent index to the hardware index by adding
@@ -368,13 +357,11 @@ static unsigned long 
ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	unsigned long rate = parent_rate;

	u32 div_reg, div;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_DIV) {

		div_reg = readl(cgu->base + clk_info->div.reg);

		div = (div_reg >> clk_info->div.shift) &
@@ -443,12 +430,9 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, 
		       unsigned long *parent_rate)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	unsigned int div = 1;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_DIV)

		div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);

	else if (clk_info->type & CGU_CLK_FIXDIV)
@@ -462,16 +446,14 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, 
		     unsigned long parent_rate)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	const unsigned timeout = 100;

	unsigned long rate, flags;

	unsigned int hw_div, div, i;

	u32 reg, mask;

	int ret = 0;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_DIV) {

		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);

		rate = DIV_ROUND_UP(parent_rate, div);
@@ -525,12 +507,10 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, 
static int ingenic_clk_enable(struct clk_hw *hw)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	unsigned long flags;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_GATE) {

		/* ungate the clock */

		spin_lock_irqsave(&cgu->lock, flags);
@@ -547,12 +527,10 @@ static int ingenic_clk_enable(struct clk_hw *hw) 
static void ingenic_clk_disable(struct clk_hw *hw)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	unsigned long flags;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_GATE) {

		/* gate the clock */

		spin_lock_irqsave(&cgu->lock, flags);
@@ -564,12 +542,10 @@ static void ingenic_clk_disable(struct clk_hw *hw) 
static int ingenic_clk_is_enabled(struct clk_hw *hw)

{

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	int enabled = 1;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_GATE)

		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);

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