x86/mm/mem_encrypt: Fix definition of PMD_FLAGS_DEC_WP (29ac40cb) · Commits · 戴 / test

The PAT bit is in different locations for 4k and 2M/1G page table entries. Add a definition for _PAGE_LARGE_CACHE_MASK to represent the three caching bits (PWT, PCD, PAT), similar to _PAGE_CACHE_MASK for 4k pages, and use it in the definition of PMD_FLAGS_DEC_WP to get the correct PAT index for write-protected pages. Fixes: ("x86/mm: Add support to encrypt the kernel in-place") Signed-off-by:

Arvind Sankar <nivedita@alum.mit.edu> Signed-off-by:

Borislav Petkov <bp@suse.de> Tested-by:

Tom Lendacky <thomas.lendacky@amd.com> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20201111160946.147341-1-nivedita@alum.mit.edu

arch/x86/include/asm/pgtable_types.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -155,6 +155,7 @@ enum page_cache_mode {
		#define _PAGE_ENC (_AT(pteval_t, sme_me_mask))

		#define _PAGE_CACHE_MASK (_PAGE_PWT \| _PAGE_PCD \| _PAGE_PAT)
		#define _PAGE_LARGE_CACHE_MASK (_PAGE_PWT \| _PAGE_PCD \| _PAGE_PAT_LARGE)

		#define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
		#define _PAGE_CACHE_WP (cachemode2protval(_PAGE_CACHE_MODE_WP))

arch/x86/mm/mem_encrypt_identity.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -45,8 +45,8 @@
		#define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)

		#define PMD_FLAGS_DEC PMD_FLAGS_LARGE
		#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) \| \
		(_PAGE_PAT \| _PAGE_PWT))
		#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_LARGE_CACHE_MASK) \| \
		(_PAGE_PAT_LARGE \| _PAGE_PWT))

		#define PMD_FLAGS_ENC (PMD_FLAGS_LARGE \| _PAGE_ENC)

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