Commit 29a0e7be authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

ARM: tegra: retain L2 content over CPU suspend/resume 



The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d552920a

arch/arm/mach-tegra/common.c

+5 −1
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#include "pmc.h"

#include "apbio.h"

#include "sleep.h"

#include "pm.h"



/*

 * Storage for debug-macro.S's state.
@@ -117,6 +118,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { 
static void __init tegra_init_cache(void)

{

#ifdef CONFIG_CACHE_L2X0

	int ret;

	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;

	u32 aux_ctrl, cache_type;
@@ -124,7 +126,9 @@ static void __init tegra_init_cache(void) 
	aux_ctrl = (cache_type & 0x700) << (17-8);

	aux_ctrl |= 0x7C400001;



	l2x0_of_init(aux_ctrl, 0x8200c3fe);

	ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);

	if (!ret)

		l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);

#endif



}

arch/arm/mach-tegra/headsmp.S

+11 −0
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 
#include <linux/init.h>



#include <asm/cache.h>

#include <asm/asm-offsets.h>

#include <asm/hardware/cache-l2x0.h>



#include "flowctrl.h"

#include "iomap.h"
@@ -113,10 +115,19 @@ ENTRY(tegra_resume) 
	str	r1, [r0]

#endif



	/* L2 cache resume & re-enable */

	l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr



	b	cpu_resume

ENDPROC(tegra_resume)

#endif



#ifdef CONFIG_CACHE_L2X0

	.globl	l2x0_saved_regs_addr

l2x0_saved_regs_addr:

	.long	0

#endif



	.align L1_CACHE_SHIFT

ENTRY(__tegra_cpu_reset_handler_start)

arch/arm/mach-tegra/pm.c

+0 −2
Original line number Diff line number Diff line
@@ -207,11 +207,9 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) 


	cpu_cluster_pm_enter();

	suspend_cpu_complex();

	outer_disable();



	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);



	outer_resume();

	restore_cpu_complex();

	cpu_cluster_pm_exit();

}

arch/arm/mach-tegra/pm.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#ifndef _MACH_TEGRA_PM_H_

#define _MACH_TEGRA_PM_H_



extern unsigned long l2x0_saved_regs_addr;



void save_cpu_arch_register(void);

void restore_cpu_arch_register(void);

arch/arm/mach-tegra/sleep.S

+7 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <asm/assembler.h>

#include <asm/cache.h>

#include <asm/cp15.h>

#include <asm/hardware/cache-l2x0.h>



#include "iomap.h"
@@ -98,6 +99,12 @@ ENTRY(tegra_shut_off_mmu) 
	dsb

	mcr	p15, 0, r3, c1, c0, 0

	isb

#ifdef CONFIG_CACHE_L2X0

	/* Disable L2 cache */

	mov32	r4, TEGRA_ARM_PERIF_BASE + 0x3000

	mov	r5, #0

	str	r5, [r4, #L2X0_CTRL]

#endif

	mov	pc, r0

ENDPROC(tegra_shut_off_mmu)

	.popsection

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