Commit 297b9ceb authored by Horia Geantă's avatar Horia Geantă Committed by Herbert Xu
Browse files

crypto: caam/jr - add support for DPAA2 parts 



Add support for using the caam/jr backend on DPAA2-based SoCs.
These have some particularities we have to account for:
-HW S/G format is different
-Management Complex (MC) firmware initializes / manages (partially)
the CAAM block: MCFGR, QI enablement in QICTL, RNG

Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent e28c190d

drivers/crypto/caam/caamhash.c

+3 −4
Original line number Diff line number Diff line
@@ -791,8 +791,8 @@ static int ahash_update_ctx(struct ahash_request *req) 
							 to_hash - *buflen,

							 *next_buflen, 0);

		} else {

			(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=

				cpu_to_caam32(SEC4_SG_LEN_FIN);

			sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index -

					    1);

		}



		desc = edesc->hw_desc;
@@ -882,8 +882,7 @@ static int ahash_final_ctx(struct ahash_request *req) 
	if (ret)

		goto unmap_ctx;



	(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=

		cpu_to_caam32(SEC4_SG_LEN_FIN);

	sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index - 1);



	edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,

					    sec4_sg_bytes, DMA_TO_DEVICE);

drivers/crypto/caam/ctrl.c

+29 −16
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 


bool caam_little_end;

EXPORT_SYMBOL(caam_little_end);

bool caam_dpaa2;

EXPORT_SYMBOL(caam_dpaa2);



#ifdef CONFIG_CAAM_QI

#include "qi.h"
@@ -319,8 +321,11 @@ static int caam_remove(struct platform_device *pdev) 
		caam_qi_shutdown(ctrlpriv->qidev);

#endif



	/* De-initialize RNG state handles initialized by this driver. */

	if (ctrlpriv->rng4_sh_init)

	/*

	 * De-initialize RNG state handles initialized by this driver.

	 * In case of DPAA 2.x, RNG is managed by MC firmware.

	 */

	if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)

		deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);



	/* Shut down debug views */
@@ -552,12 +557,17 @@ static int caam_probe(struct platform_device *pdev) 


	/*

	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,

	 * long pointers in master configuration register

	 * long pointers in master configuration register.

	 * In case of DPAA 2.x, Management Complex firmware performs

	 * the configuration.

	 */

	caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);

	if (!caam_dpaa2)

		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,

			      MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |

			      MCFGR_WDENABLE | MCFGR_LARGE_BURST |

		      (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));

			      (sizeof(dma_addr_t) == sizeof(u64) ?

			       MCFGR_LONG_PTR : 0));



	/*

	 *  Read the Compile Time paramters and SCFGR to determine
@@ -586,7 +596,9 @@ static int caam_probe(struct platform_device *pdev) 
			      JRSTART_JR3_START);



	if (sizeof(dma_addr_t) == sizeof(u64)) {

		if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))

		if (caam_dpaa2)

			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));

		else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))

			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));

		else

			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
@@ -629,11 +641,9 @@ static int caam_probe(struct platform_device *pdev) 
			ring++;

		}



	/* Check to see if QI present. If so, enable */

	ctrlpriv->qi_present =

			!!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &

			   CTPR_MS_QI_MASK);

	if (ctrlpriv->qi_present) {

	/* Check to see if (DPAA 1.x) QI present. If so, enable */

	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);

	if (ctrlpriv->qi_present && !caam_dpaa2) {

		ctrlpriv->qi = (struct caam_queue_if __iomem __force *)

			       ((__force uint8_t *)ctrl +

				 BLOCK_OFFSET * QI_BLOCK_NUMBER
@@ -661,8 +671,10 @@ static int caam_probe(struct platform_device *pdev) 
	/*

	 * If SEC has RNG version >= 4 and RNG state handle has not been

	 * already instantiated, do RNG instantiation

	 * In case of DPAA 2.x, RNG is managed by MC firmware.

	 */

	if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {

	if (!caam_dpaa2 &&

	    (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {

		ctrlpriv->rng4_sh_init =

			rd_reg32(&ctrl->r4tst[0].rdsta);

		/*
@@ -730,8 +742,9 @@ static int caam_probe(struct platform_device *pdev) 
	/* Report "alive" for developer to see */

	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,

		 caam_get_era());

	dev_info(dev, "job rings = %d, qi = %d\n",

		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);

	dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",

		 ctrlpriv->total_jobrs, ctrlpriv->qi_present,

		 caam_dpaa2 ? "yes" : "no");



#ifdef CONFIG_DEBUG_FS

drivers/crypto/caam/ctrl.h

+2 −0
Original line number Diff line number Diff line
@@ -10,4 +10,6 @@ 
/* Prototypes for backend-level services exposed to APIs */

int caam_get_era(void);



extern bool caam_dpaa2;



#endif /* CTRL_H */

drivers/crypto/caam/jr.c

+6 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/of_address.h>



#include "compat.h"

#include "ctrl.h"

#include "regs.h"

#include "jr.h"

#include "desc.h"
@@ -499,7 +500,11 @@ static int caam_jr_probe(struct platform_device *pdev) 
	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;



	if (sizeof(dma_addr_t) == sizeof(u64)) {

		if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))

		if (caam_dpaa2)

			error = dma_set_mask_and_coherent(jrdev,

							  DMA_BIT_MASK(49));

		else if (of_device_is_compatible(nprop,

						 "fsl,sec-v5.0-job-ring"))

			error = dma_set_mask_and_coherent(jrdev,

							  DMA_BIT_MASK(40));

		else

drivers/crypto/caam/regs.h

+1 −0
Original line number Diff line number Diff line
@@ -293,6 +293,7 @@ struct caam_perfmon { 
	u32 cha_rev_ls;		/* CRNR - CHA Rev No. Least significant half*/

#define CTPR_MS_QI_SHIFT	25

#define CTPR_MS_QI_MASK		(0x1ull << CTPR_MS_QI_SHIFT)

#define CTPR_MS_DPAA2		BIT(13)

#define CTPR_MS_VIRT_EN_INCL	0x00000001

#define CTPR_MS_VIRT_EN_POR	0x00000002

#define CTPR_MS_PG_SZ_MASK	0x10

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