Commit 296c9120 authored by Stefan Roese's avatar Stefan Roese Committed by David S. Miller
Browse files

net: ethernet: mediatek: Add MT7628/88 SoC support 



This patch adds support for the MediaTek MT7628/88 SoCs to the common
MediaTek ethernet driver. Some minor changes are needed for this and
a bigger change, as the MT7628 does not support QDMA (only PDMA).

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Cc: René van Dorst <opensource@vdorst.com>
Cc: Daniel Golle <daniel@makrotopia.org>
Cc: Sean Wang <sean.wang@mediatek.com>
Cc: John Crispin <john@phrozen.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 08df5fa6

drivers/net/ethernet/mediatek/Kconfig

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

config NET_VENDOR_MEDIATEK

	bool "MediaTek ethernet driver"

	depends on ARCH_MEDIATEK || SOC_MT7621

	depends on ARCH_MEDIATEK || SOC_MT7621 || SOC_MT7620

	---help---

	  If you have a Mediatek SoC with ethernet, say Y.

drivers/net/ethernet/mediatek/mtk_eth_path.c

+4 −0
Original line number Diff line number Diff line
@@ -315,6 +315,10 @@ int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode) 
{

	int err;



	/* No mux'ing for MT7628/88 */

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))

		return 0;



	switch (phymode) {

	case PHY_INTERFACE_MODE_TRGMII:

	case PHY_INTERFACE_MODE_RGMII_TXID:

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+373 −107

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+47 −4
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
				 NETIF_F_SG | NETIF_F_TSO | \

				 NETIF_F_TSO6 | \

				 NETIF_F_IPV6_CSUM)

#define MTK_HW_FEATURES_MT7628	(NETIF_F_SG | NETIF_F_RXCSUM)

#define NEXT_DESP_IDX(X, Y)	(((X) + 1) & ((Y) - 1))



#define MTK_MAX_RX_RING_NUM	4
@@ -118,6 +119,7 @@ 
/* PDMA Global Configuration Register */

#define MTK_PDMA_GLO_CFG	0xa04

#define MTK_MULTI_EN		BIT(10)

#define MTK_PDMA_SIZE_8DWORDS	(1 << 4)



/* PDMA Reset Index Register */

#define MTK_PDMA_RST_IDX	0xa08
@@ -276,11 +278,18 @@ 
#define TX_DMA_OWNER_CPU	BIT(31)

#define TX_DMA_LS0		BIT(30)

#define TX_DMA_PLEN0(_x)	(((_x) & MTK_TX_DMA_BUF_LEN) << 16)

#define TX_DMA_PLEN1(_x)	((_x) & MTK_TX_DMA_BUF_LEN)

#define TX_DMA_SWC		BIT(14)

#define TX_DMA_SDL(_x)		(((_x) & 0x3fff) << 16)



/* PDMA on MT7628 */

#define TX_DMA_DONE		BIT(31)

#define TX_DMA_LS1		BIT(14)

#define TX_DMA_DESP2_DEF	(TX_DMA_LS0 | TX_DMA_DONE)



/* QDMA descriptor rxd2 */

#define RX_DMA_DONE		BIT(31)

#define RX_DMA_LSO		BIT(30)

#define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)

#define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)
@@ -289,6 +298,7 @@ 


/* QDMA descriptor rxd4 */

#define RX_DMA_L4_VALID		BIT(24)

#define RX_DMA_L4_VALID_PDMA	BIT(30)		/* when PDMA is used */

#define RX_DMA_FPORT_SHIFT	19

#define RX_DMA_FPORT_MASK	0x7
@@ -412,6 +422,19 @@ 
#define CO_QPHY_SEL            BIT(0)

#define GEPHY_MAC_SEL          BIT(1)



/* MT7628/88 specific stuff */

#define MT7628_PDMA_OFFSET	0x0800

#define MT7628_SDM_OFFSET	0x0c00



#define MT7628_TX_BASE_PTR0	(MT7628_PDMA_OFFSET + 0x00)

#define MT7628_TX_MAX_CNT0	(MT7628_PDMA_OFFSET + 0x04)

#define MT7628_TX_CTX_IDX0	(MT7628_PDMA_OFFSET + 0x08)

#define MT7628_TX_DTX_IDX0	(MT7628_PDMA_OFFSET + 0x0c)

#define MT7628_PST_DTX_IDX0	BIT(0)



#define MT7628_SDM_MAC_ADRL	(MT7628_SDM_OFFSET + 0x0c)

#define MT7628_SDM_MAC_ADRH	(MT7628_SDM_OFFSET + 0x10)



struct mtk_rx_dma {

	unsigned int rxd1;

	unsigned int rxd2;
@@ -509,6 +532,7 @@ enum mtk_clks_map { 
				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL))

#define MT7621_CLKS_BITMAP	(0)

#define MT7628_CLKS_BITMAP	(0)

#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
@@ -563,6 +587,10 @@ struct mtk_tx_ring { 
	struct mtk_tx_dma *last_free;

	u16 thresh;

	atomic_t free_count;

	int dma_size;

	struct mtk_tx_dma *dma_pdma;	/* For MT7628/88 PDMA handling */

	dma_addr_t phys_pdma;

	int cpu_idx;

};



/* PDMA rx ring mode */
@@ -604,6 +632,8 @@ enum mkt_eth_capabilities { 
	MTK_HWLRO_BIT,

	MTK_SHARED_INT_BIT,

	MTK_TRGMII_MT7621_CLK_BIT,

	MTK_QDMA_BIT,

	MTK_SOC_MT7628_BIT,



	/* MUX BITS*/

	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
@@ -634,6 +664,8 @@ enum mkt_eth_capabilities { 
#define MTK_HWLRO		BIT(MTK_HWLRO_BIT)

#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)

#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)

#define MTK_QDMA		BIT(MTK_QDMA_BIT)

#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)



#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\

	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
@@ -687,26 +719,31 @@ enum mkt_eth_capabilities { 
#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))



#define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \

		      MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK)

		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \

		      MTK_TRGMII_MT7621_CLK | MTK_QDMA)



#define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \

		      MTK_GMAC2_SGMII | MTK_GDM1_ESW | \

		      MTK_MUX_GDM1_TO_GMAC1_ESW | \

		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII)

		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)



#define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \

		      MTK_QDMA)



#define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII)

#define MT7628_CAPS  (MTK_SHARED_INT | MTK_SOC_MT7628)



#define MT7629_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \

		      MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \

		      MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \

		      MTK_MUX_U3_GMAC2_TO_QPHY | \

		      MTK_MUX_GMAC12_TO_GEPHY_SGMII)

		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)



/* struct mtk_eth_data -	This is the structure holding all differences

 *				among various plaforms

 * @ana_rgc3:                   The offset for register ANA_RGC3 related to

 *				sgmiisys syscon

 * @caps			Flags shown the extra capability for the SoC

 * @hw_features			Flags shown HW features

 * @required_clks		Flags shown the bitmap for required clocks on

 *				the target SoC

 * @required_pctl		A bool value to show whether the SoC requires
@@ -717,6 +754,7 @@ struct mtk_soc_data { 
	u32		caps;

	u32		required_clks;

	bool		required_pctl;

	netdev_features_t hw_features;

};



/* currently no SoC has more than 2 macs */
@@ -810,6 +848,11 @@ struct mtk_eth { 
	unsigned long			state;



	const struct mtk_soc_data	*soc;



	u32				tx_int_mask_reg;

	u32				tx_int_status_reg;

	u32				rx_dma_l4_valid;

	int				ip_align;

};



/* struct mtk_mac -	the structure that holds the info about the MACs of the

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