Commit 29430fae authored by Alastair D'Silva's avatar Alastair D'Silva Committed by Michael Ellerman
Browse files

powerpc: Allow flush_icache_range to work across ranges >4GB 



When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.

This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.

Signed-off-by: default avatarAlastair D'Silva <alastair@d-silva.org>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20191104023305.9581-2-alastair@au1.ibm.com
parent d79fbb3a

arch/powerpc/kernel/misc_64.S

+2 −2
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of cache block size */

	srw.	r8,r8,r9		/* compute line count */

	srd.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mtctr	r8

1:	dcbst	0,r6
@@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5

	lwz	r9,ICACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of Icache block size */

	srw.	r8,r8,r9		/* compute line count */

	srd.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mtctr	r8

2:	icbi	0,r6

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