ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level (292a3546) · Commits · 戴 / test

For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree. Signed-off-by:

arch/arm/boot/dts/armada-370.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -129,6 +129,7 @@
		compatible = "marvell,aurora-outer-cache";
		reg = <0x08000 0x1000>;
		cache-id-part = <0x100>;
		cache-level = <2>;
		cache-unified;
		wt-override;
		};

+1 −0

Original line number	Diff line number	Diff line
		@@ -79,6 +79,7 @@
		compatible = "marvell,aurora-system-cache";
		reg = <0x08000 0x1000>;
		cache-id-part = <0x100>;
		cache-level = <2>;
		cache-unified;
		wt-override;
		};