Commit 290a9f93 authored by Fabien Dessenne's avatar Fabien Dessenne Committed by Linus Walleij
Browse files

pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API 



Use the hwspin_lock_timeout_in_atomic() API which is the most appropriated
here. Indeed:
- hwspin_lock_() is called after spin_lock_irqsave()
- the hwspin_lock_timeout() API relies on jiffies count which won't work
  if IRQs are disabled which is the case here.

Signed-off-by: default avatarFabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
Link: https://lore.kernel.org/r/20200615124456.27328-1-alexandre.torgue@st.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 57597e15

drivers/pinctrl/stm32/pinctrl-stm32.c

+42 −36
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ 
#define gpio_range_to_bank(chip) \

		container_of(chip, struct stm32_gpio_bank, range)



#define HWSPINLOCK_TIMEOUT	5 /* msec */

#define HWSPNLCK_TIMEOUT	1000 /* usec */



static const char * const stm32_gpio_functions[] = {

	"gpio", "af0", "af1",
@@ -422,20 +422,22 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, 
	 * to avoid overriding.

	 */

	spin_lock_irqsave(&pctl->irqmux_lock, flags);

	if (pctl->hwlock)

		ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);



	if (pctl->hwlock) {

		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,

						    HWSPNLCK_TIMEOUT);

		if (ret) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	if (pctl->irqmux_map & BIT(irq_data->hwirq)) {

		dev_err(pctl->dev, "irq line %ld already requested.\n",

			irq_data->hwirq);

		ret = -EBUSY;

		if (pctl->hwlock)

			hwspin_unlock(pctl->hwlock);

			hwspin_unlock_in_atomic(pctl->hwlock);

		goto unlock;

	} else {

		pctl->irqmux_map |= BIT(irq_data->hwirq);
@@ -444,7 +446,7 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, 
	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);



	if (pctl->hwlock)

		hwspin_unlock(pctl->hwlock);

		hwspin_unlock_in_atomic(pctl->hwlock);



unlock:

	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
@@ -752,13 +754,14 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 
	clk_enable(bank->clk);

	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock)

		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,

						    HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	val = readl_relaxed(bank->base + alt_offset);

	val &= ~GENMASK(alt_shift + 3, alt_shift);
@@ -771,7 +774,7 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 
	writel_relaxed(val, bank->base + STM32_GPIO_MODER);



	if (pctl->hwlock)

		hwspin_unlock(pctl->hwlock);

		hwspin_unlock_in_atomic(pctl->hwlock);



	stm32_gpio_backup_mode(bank, pin, mode, alt);
@@ -871,13 +874,14 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 
	clk_enable(bank->clk);

	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock)

		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,

						    HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);

	val &= ~BIT(offset);
@@ -885,7 +889,7 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 
	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);



	if (pctl->hwlock)

		hwspin_unlock(pctl->hwlock);

		hwspin_unlock_in_atomic(pctl->hwlock);



	stm32_gpio_backup_driving(bank, offset, drive);
@@ -925,13 +929,14 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 
	clk_enable(bank->clk);

	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock)

		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,

						    HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);

	val &= ~GENMASK(offset * 2 + 1, offset * 2);
@@ -939,7 +944,7 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 
	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);



	if (pctl->hwlock)

		hwspin_unlock(pctl->hwlock);

		hwspin_unlock_in_atomic(pctl->hwlock);



	stm32_gpio_backup_speed(bank, offset, speed);
@@ -979,13 +984,14 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 
	clk_enable(bank->clk);

	spin_lock_irqsave(&bank->lock, flags);



	if (pctl->hwlock)

		err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);



	if (pctl->hwlock) {

		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,

						    HWSPNLCK_TIMEOUT);

		if (err) {

			dev_err(pctl->dev, "Can't get hwspinlock\n");

			goto unlock;

		}

	}



	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);

	val &= ~GENMASK(offset * 2 + 1, offset * 2);
@@ -993,7 +999,7 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 
	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);



	if (pctl->hwlock)

		hwspin_unlock(pctl->hwlock);

		hwspin_unlock_in_atomic(pctl->hwlock);



	stm32_gpio_backup_bias(bank, offset, bias);

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