drm/amd/display: Change the delay time before enabling FEC (28fa24ad) · Commits · 戴 / test

[why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by:

Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:

Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:

Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -3522,7 +3522,14 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
		if (link_enc->funcs->fec_set_enable &&
		link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
		if (link->fec_state == dc_link_fec_ready && enable) {
		msleep(1);
		/* Accord to DP spec, FEC enable sequence can first
		* be transmitted anytime after 1000 LL codes have
		* been transmitted on the link after link training
		* completion. Using 1 lane RBR should have the maximum
		* time for transmitting 1000 LL codes which is 6.173 us.
		* So use 7 microseconds delay instead.
		*/
		udelay(7);
		link_enc->funcs->fec_set_enable(link_enc, true);
		link->fec_state = dc_link_fec_enabled;
		} else if (link->fec_state == dc_link_fec_enabled && !enable) {

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