Commit 28f87950 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: clear ras controller status registers when interrupt occurs 



To fix issue that ras controller interrupt cannot be triggered anymore after
one time nbif uncorrectable error. And error count is stored in nbif ras object
for query.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2a79be1

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+10 −0
Original line number Diff line number Diff line
@@ -52,6 +52,9 @@ 
#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL

#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L



static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,

					void *ras_error_status);



static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)

{

	uint32_t bif_doorbell_intr_cntl;

	struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);



	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device 
						RAS_CNTLR_INTERRUPT_CLEAR, 1);

		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);



		/*

		 * clear error status after ras_controller_intr according to

		 * hw team and count ue number for query

		 */

		nbio_v7_4_query_ras_error_count(adev, &obj->err_data);



		DRM_WARN("RAS controller interrupt triggered by NBIF error\n");



		/* ras_controller_int is dedicated for nbif ras error,

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