Commit 28dce7c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC architecture updates from Vineet Gupta:
 "ARC updates for 4.3:

   - perf support for ARCv2 based cores (sampling interrupt, SMP)
   - leftovers for ARCv2 support
   - futex fixes"

* tag 'arc-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARCv2: entry: Fix reserved handler
  ARCv2: perf: Finally introduce HS perf unit
  ARCv2: perf: SMP support
  ARCv2: perf: implement exclusion of event counting in user or kernel mode
  ARCv2: perf: Support sampling events using overflow interrupts
  ARCv2: perf: implement "event_set_period"
  ARC: perf: cap the number of counters to hardware max of 32
  ARC: Eliminate some ARCv2 specific code for ARCompact build
  ARC: add/fix some comments in code - no functional change
  ARC: change some branchs to jumps to resolve linkage errors
  ARC: ensure futex ops are atomic in !LLSC config
  ARC: Enable HAVE_FUTEX_CMPXCHG
  ARC: make futex_atomic_cmpxchg_inatomic() return bimodal
  ARC: futex cosmetics
  ARC: add barriers to futex code
  ARCv2: IOC: Allow boot time disable
  ARCv2: SLC: Allow boot time disable
  ARCv2: Support IO Coherency and permutations involving L1 and L2 caches
  ARC: Enable optimistic spinning for LLSC config
  MAINTAINERS: add git tree for the arc architecture
parents 361f7d17 3d592659

Documentation/devicetree/bindings/arc/archs-pct.txt

0 → 100644
+17 −0
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* ARC HS Performance Counters



The ARC HS can be configured with a pipeline performance monitor for counting

CPU and cache events like cache misses and hits. Like conventional PCT there

are 100+ hardware conditions dynamically mapped to upto 32 counters.

It also supports overflow interrupts.



Required properties:



- compatible : should contain

	"snps,archs-pct"



Example:



pmu {

        compatible = "snps,archs-pct";

};

MAINTAINERS

+2 −1
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@@ -9911,8 +9911,9 @@ SYNOPSYS ARC ARCHITECTURE 
M:	Vineet Gupta <vgupta@synopsys.com>

S:	Supported

F:	arch/arc/

F:	Documentation/devicetree/bindings/arc/

F:	Documentation/devicetree/bindings/arc/*

F:	drivers/tty/serial/arc_uart.c

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git



SYNOPSYS ARC SDP platform support

M:	Alexey Brodkin <abrodkin@synopsys.com>

arch/arc/Kconfig

+2 −0
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@@ -8,6 +8,7 @@ 


config ARC

	def_bool y

	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC

	select BUILDTIME_EXTABLE_SORT

	select COMMON_CLK

	select CLONE_BACKWARDS
@@ -22,6 +23,7 @@ config ARC 
	select GENERIC_SMP_IDLE_THREAD

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_TRACEHOOK

	select HAVE_FUTEX_CMPXCHG

	select HAVE_IOREMAP_PROT

	select HAVE_KPROBES

	select HAVE_KRETPROBES

arch/arc/boot/dts/axc003.dtsi

+7 −6
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@@ -72,12 +72,13 @@ 
	};



	/*

	 * This INTC is actually connected to DW APB GPIO

	 * which acts as a wire between MB INTC and CPU INTC.

	 * GPIO INTC is configured in platform init code

	 * and here we mimic direct connection from MB INTC to

	 * CPU INTC, thus we set "interrupts = <7>" instead of

	 * "interrupts = <12>"

	 * The DW APB ICTL intc on MB is connected to CPU intc via a

	 * DT "invisible" DW APB GPIO block, configured to simply pass thru

	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)

	 *

	 * So here we mimic a direct connection betwen them, ignoring the

	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)

	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)

	 *

	 * This intc actually resides on MB, but we move it here to

	 * avoid duplicating the MB dtsi file given that IRQ from

arch/arc/include/asm/arcregs.h

+1 −0
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@@ -35,6 +35,7 @@ 
#define ARC_REG_RTT_BCR		0xF2

#define ARC_REG_IRQ_BCR		0xF3

#define ARC_REG_SMART_BCR	0xFF

#define ARC_REG_CLUSTER_BCR	0xcf



/* status32 Bits Positions */

#define STATUS_AE_BIT		5	/* Exception active */

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