Merge master.kernel.org:/home/rmk/linux-2.6-arm (28c006c1) · Commits · 戴 / test

arch/arm/mach-realview/core.c

+2 −26

Original line number	Diff line number	Diff line
		@@ -202,11 +202,6 @@ struct clk realview_clcd_clk = {
		/*
		* CLCD support.
		*/
		#define SYS_CLCD_MODE_MASK (3 << 0)
		#define SYS_CLCD_MODE_888 (0 << 0)
		#define SYS_CLCD_MODE_5551 (1 << 0)
		#define SYS_CLCD_MODE_565_RLSB (2 << 0)
		#define SYS_CLCD_MODE_565_BLSB (3 << 0)
		#define SYS_CLCD_NLCDIOON (1 << 2)
		#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
		#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
		@@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb)
		void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
		u32 val;

		val = readl(sys_clcd);
		val &= ~SYS_CLCD_MODE_MASK;

		switch (fb->fb.var.green.length) {
		case 5:
		val \|= SYS_CLCD_MODE_5551;
		break;
		case 6:
		val \|= SYS_CLCD_MODE_565_RLSB;
		break;
		case 8:
		val \|= SYS_CLCD_MODE_888;
		break;
		}

		/*
		* Set the MUX
		*/
		writel(val, sys_clcd);

		/*
		* And now enable the PSUs
		* Enable the PSUs
		*/
		val = readl(sys_clcd);
		val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
		writel(val, sys_clcd);
		}

+1 −1

Original line number	Diff line number	Diff line
		@@ -27,7 +27,7 @@ extern void enable_irq(unsigned int);

		/*
		* These correspond with the SA_TRIGGER_* defines, and therefore the
		* IRQRESOURCE_IRQ_* defines.
		* IORESOURCE_IRQ_* defines.
		*/
		#define __IRQT_RISEDGE (1 << 0)
		#define __IRQT_FALEDGE (1 << 1)

+11 −1

Original line number	Diff line number	Diff line
		@@ -54,6 +54,7 @@
		#define CNTL_LCDBPP4 (2 << 1)
		#define CNTL_LCDBPP8 (3 << 1)
		#define CNTL_LCDBPP16 (4 << 1)
		#define CNTL_LCDBPP16_565 (6 << 1)
		#define CNTL_LCDBPP24 (5 << 1)
		#define CNTL_LCDBW (1 << 4)
		#define CNTL_LCDTFT (1 << 5)
		@@ -209,7 +210,16 @@ static inline void clcdfb_decode(struct clcd_fb fb, struct clcd_regs regs)
		val \|= CNTL_LCDBPP8;
		break;
		case 16:
		/*
		* PL110 cannot choose between 5551 and 565 modes in
		* its control register
		*/
		if ((fb->dev->periphid & 0x000fffff) == 0x00041110)
		val \|= CNTL_LCDBPP16;
		else if (fb->fb.var.green.length == 5)
		val \|= CNTL_LCDBPP16;
		else
		val \|= CNTL_LCDBPP16_565;
		break;
		case 32:
		val \|= CNTL_LCDBPP24;