Commit 289991ce authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2019-09-27' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Fixes built up over the past 1.5 weeks or so, it's two weeks of
  amdgpu, some core cleanups and some panfrost fixes. I also finally
  figured out why my desktop was slow to do a bunch of stuff (someone
  gave it an IPv6 address which can't reach anything!).

  core:
   - Some cleanups and fixes in the self-refresh helpers
   - Some cleanups and fixes in the atomic helpers

  amdgpu:
   - Fix a 64 bit divide
   - Prevent a memory leak in a failure case in dc
   - Load proper gfx firmware on navi14 variants
   - Add more navi12 and navi14 PCI ids
   - Misc fixes for renoir
   - Fix bandwidth issues with multiple displays on vega20
   - Support for Dali
   - Fix a possible oops with KFD on hawaii
   - Fix for backlight level after resume on some APUs
   - Other misc fixes

  panfrost:
   - Multiple panfrost fixes for regulator support and page fault
     handling"

* tag 'drm-next-2019-09-27' of git://anongit.freedesktop.org/drm/drm: (34 commits)
  drm/amd/display: prevent memory leak
  drm/amdgpu/gfx10: add support for wks firmware loading
  drm/amdgpu/display: include slab.h in dcn21_resource.c
  drm/amdgpu/display: fix 64 bit divide
  drm/panfrost: Prevent race when handling page fault
  drm/panfrost: Remove NULL checks for regulator
  drm/panfrost: Fix regulator_get_optional() misuse
  drm: Measure Self Refresh Entry/Exit times to avoid thrashing
  drm: Fix kerneldoc and remove unused struct member in self_refresh helper
  drm/atomic: Rename crtc_state->pageflip_flags to async_flip
  drm/atomic: Reject FLIP_ASYNC unconditionally
  drm/atomic: Take the atomic toys away from X
  drm/amdgpu: flag navi12 and 14 as experimental for 5.4
  drm/kms: Duct-tape for mode object lifetime checks
  drm/amdgpu: add navi12 pci id
  drm/amdgpu: add navi14 PCI ID for work station SKU
  drm/amdkfd: Swap trap temporary registers in gfx10 trap handler
  drm/amd/powerplay: implement sysfs for getting dpm clock
  drm/amd/display: Restore backlight brightness after system resume
  drm/amd/display: Implement voltage limitation for dali
  ...
parents 0cd81d77 3e2cb6d8

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c

+1 −1
Original line number Diff line number Diff line
@@ -948,6 +948,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block 
	case AMD_IP_BLOCK_TYPE_UVD:

	case AMD_IP_BLOCK_TYPE_VCN:

	case AMD_IP_BLOCK_TYPE_VCE:

	case AMD_IP_BLOCK_TYPE_SDMA:

		if (swsmu)

			ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);

		else
@@ -956,7 +957,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block 
		break;

	case AMD_IP_BLOCK_TYPE_GMC:

	case AMD_IP_BLOCK_TYPE_ACP:

	case AMD_IP_BLOCK_TYPE_SDMA:

		ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(

				(adev)->powerplay.pp_handle, block_type, gate));

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+6 −1
Original line number Diff line number Diff line
@@ -1012,11 +1012,16 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},

	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},

	/* Navi14 */

	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},

	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},



	/* Renoir */

	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},



	/* Navi12 */

	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},



	{0, 0, 0}

};

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+2 −1
Original line number Diff line number Diff line
@@ -143,7 +143,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	/* ring tests don't use a job */

	if (job) {

		vm = job->vm;

		fence_ctx = job->base.s_fence->scheduled.context;

		fence_ctx = job->base.s_fence ?

			job->base.s_fence->scheduled.context : 0;

	} else {

		vm = NULL;

		fence_ctx = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+3 −0
Original line number Diff line number Diff line
@@ -677,6 +677,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)

			sh_num = 0xffffffff;



		if (info->read_mmr_reg.count > 128)

			return -EINVAL;



		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);

		if (!regs)

			return -ENOMEM;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −6
Original line number Diff line number Diff line
@@ -70,6 +70,11 @@ MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 
MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");

MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");



MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");

MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");

MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");

MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");

MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");

MODULE_FIRMWARE("amdgpu/navi14_ce.bin");

MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");

MODULE_FIRMWARE("amdgpu/navi14_me.bin");
@@ -594,7 +599,8 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 
static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)

{

	const char *chip_name;

	char fw_name[30];

	char fw_name[40];

	char wks[10];

	int err;

	struct amdgpu_firmware_info *info = NULL;

	const struct common_firmware_header *header = NULL;
@@ -607,12 +613,16 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 


	DRM_DEBUG("\n");



	memset(wks, 0, sizeof(wks));

	switch (adev->asic_type) {

	case CHIP_NAVI10:

		chip_name = "navi10";

		break;

	case CHIP_NAVI14:

		chip_name = "navi14";

		if (!(adev->pdev->device == 0x7340 &&

		      adev->pdev->revision != 0x00))

			snprintf(wks, sizeof(wks), "_wks");

		break;

	case CHIP_NAVI12:

		chip_name = "navi12";
@@ -621,7 +631,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
		BUG();

	}



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);

	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);

	if (err)

		goto out;
@@ -632,7 +642,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);

	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);

	if (err)

		goto out;
@@ -643,7 +653,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);

	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);

	if (err)

		goto out;
@@ -708,7 +718,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
	if (adev->gfx.rlc.is_rlc_v2_1)

		gfx_v10_0_init_rlc_ext_microcode(adev);



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);

	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);

	if (err)

		goto out;
@@ -719,7 +729,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);



	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);

	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);

	if (!err) {

		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);

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