clk: sunxi-ng: h6: fix bus clocks' divider position (2852bfbf) · Commits · 戴 / test

The bus clocks (AHB/APB) on Allwinner H6 have their second divider start at bit 8, according to the user manual and the BSP code. However, currently the divider offset is incorrectly set to 16, thus the divider is not correctly read and the clock frequency is not correctly calculated. Fix this bit offset on all affected bus clocks in ccu-sun50i-h6. Cc: stable@vger.kernel.org # v4.17.y Signed-off-by:

Icenowy Zheng <icenowy@aosc.io> Signed-off-by:

Chen-Yu Tsai <wens@csie.org>

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -224,7 +224,7 @@ static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
		psi_ahb1_ahb2_parents,
		0x510,
		0, 5, /* M */
		16, 2, /* P */
		8, 2, /* P */
		24, 2, /* mux */
		0);

		@@ -233,19 +233,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
		"pll-periph0" };
		static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
		0, 5, /* M */
		16, 2, /* P */
		8, 2, /* P */
		24, 2, /* mux */
		0);

		static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
		0, 5, /* M */
		16, 2, /* P */
		8, 2, /* P */
		24, 2, /* mux */
		0);

		static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
		0, 5, /* M */
		16, 2, /* P */
		8, 2, /* P */
		24, 2, /* mux */
		0);

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