Merge branch 'master' of git://git.infradead.org/users/rafal/b43-next (27eee235) · Commits · 戴 / test

drivers/net/wireless/b43/phy_ht.c

+77 −42

Original line number	Diff line number	Diff line
		@@ -30,6 +30,17 @@
		#include "radio_2059.h"
		#include "main.h"

		/* Force values to keep compatibility with wl */
		enum ht_rssi_type {
		HT_RSSI_W1 = 0,
		HT_RSSI_W2 = 1,
		HT_RSSI_NB = 2,
		HT_RSSI_IQ = 3,
		HT_RSSI_TSSI_2G = 4,
		HT_RSSI_TSSI_5G = 5,
		HT_RSSI_TBD = 6,
		};

		/**************************************************
		* Radio 2059.
		**************************************************/
		@@ -37,8 +48,9 @@
		static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
		const struct b43_phy_ht_channeltab_e_radio2059 *e)
		{
		u8 i;
		u16 routing;
		static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
		u16 r;
		int core;

		b43_radio_write(dev, 0x16, e->radio_syn16);
		b43_radio_write(dev, 0x17, e->radio_syn17);
		@@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
		b43_radio_write(dev, 0x41, e->radio_syn41);
		b43_radio_write(dev, 0x43, e->radio_syn43);
		b43_radio_write(dev, 0x47, e->radio_syn47);
		b43_radio_write(dev, 0x4a, e->radio_syn4a);
		b43_radio_write(dev, 0x58, e->radio_syn58);
		b43_radio_write(dev, 0x5a, e->radio_syn5a);
		b43_radio_write(dev, 0x6a, e->radio_syn6a);
		b43_radio_write(dev, 0x6d, e->radio_syn6d);
		b43_radio_write(dev, 0x6e, e->radio_syn6e);
		b43_radio_write(dev, 0x92, e->radio_syn92);
		b43_radio_write(dev, 0x98, e->radio_syn98);

		for (i = 0; i < 2; i++) {
		routing = i ? R2059_RXRX1 : R2059_TXRX0;
		b43_radio_write(dev, routing \| 0x4a, e->radio_rxtx4a);
		b43_radio_write(dev, routing \| 0x58, e->radio_rxtx58);
		b43_radio_write(dev, routing \| 0x5a, e->radio_rxtx5a);
		b43_radio_write(dev, routing \| 0x6a, e->radio_rxtx6a);
		b43_radio_write(dev, routing \| 0x6d, e->radio_rxtx6d);
		b43_radio_write(dev, routing \| 0x6e, e->radio_rxtx6e);
		b43_radio_write(dev, routing \| 0x92, e->radio_rxtx92);
		b43_radio_write(dev, routing \| 0x98, e->radio_rxtx98);

		for (core = 0; core < 3; core++) {
		r = routing[core];
		b43_radio_write(dev, r \| 0x4a, e->radio_rxtx4a);
		b43_radio_write(dev, r \| 0x58, e->radio_rxtx58);
		b43_radio_write(dev, r \| 0x5a, e->radio_rxtx5a);
		b43_radio_write(dev, r \| 0x6a, e->radio_rxtx6a);
		b43_radio_write(dev, r \| 0x6d, e->radio_rxtx6d);
		b43_radio_write(dev, r \| 0x6e, e->radio_rxtx6e);
		b43_radio_write(dev, r \| 0x92, e->radio_rxtx92);
		b43_radio_write(dev, r \| 0x98, e->radio_rxtx98);
		}

		udelay(50);
		@@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,

		static void b43_radio_2059_init(struct b43_wldev *dev)
		{
		const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
		const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
		const u16 radio_values[3][2] = {
		{ 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
		};
		@@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
		b43_radio_mask(dev, 0xc0, ~0x0080);

		if (1) { /* FIXME */
		b43_radio_set(dev, R2059_RXRX1 \| 0x4, 0x1);
		b43_radio_set(dev, R2059_C3 \| 0x4, 0x1);
		udelay(10);
		b43_radio_set(dev, R2059_RXRX1 \| 0x0BF, 0x1);
		b43_radio_maskset(dev, R2059_RXRX1 \| 0x19B, 0x3, 0x2);
		b43_radio_set(dev, R2059_C3 \| 0x0BF, 0x1);
		b43_radio_maskset(dev, R2059_C3 \| 0x19B, 0x3, 0x2);

		b43_radio_set(dev, R2059_RXRX1 \| 0x4, 0x2);
		b43_radio_set(dev, R2059_C3 \| 0x4, 0x2);
		udelay(100);
		b43_radio_mask(dev, R2059_RXRX1 \| 0x4, ~0x2);
		b43_radio_mask(dev, R2059_C3 \| 0x4, ~0x2);

		for (i = 0; i < 10000; i++) {
		if (b43_radio_read(dev, R2059_RXRX1 \| 0x145) & 1) {
		if (b43_radio_read(dev, R2059_C3 \| 0x145) & 1) {
		i = 0;
		break;
		}
		@@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
		if (i)
		b43err(dev->wl, "radio 0x945 timeout\n");

		b43_radio_mask(dev, R2059_RXRX1 \| 0x4, ~0x1);
		b43_radio_mask(dev, R2059_C3 \| 0x4, ~0x1);
		b43_radio_set(dev, 0xa, 0x60);

		for (i = 0; i < 3; i++) {
		@@ -390,14 +394,14 @@ static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
		**************************************************/

		static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
		u8 rssi_type)
		enum ht_rssi_type rssi_type)
		{
		static const u16 ctl_regs[3][2] = {
		{ B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
		{ B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
		{ B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
		};
		static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, };
		static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
		int core;

		if (core_sel == 0) {
		@@ -411,13 +415,13 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
		continue;

		switch (rssi_type) {
		case 4:
		case HT_RSSI_TSSI_2G:
		b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
		b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
		b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
		b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);

		b43_radio_set(dev, R2059_RXRX1 \| 0xbf, 0x1);
		b43_radio_set(dev, R2059_C3 \| 0xbf, 0x1);
		b43_radio_write(dev, radio_r[core] \| 0x159,
		0x11);
		break;
		@@ -429,8 +433,8 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
		}
		}

		static void b43_phy_ht_poll_rssi(struct b43_wldev dev, u8 type, s32 buf,
		u8 nsamp)
		static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
		s32 *buf, u8 nsamp)
		{
		u16 phy_regs_values[12];
		static const u16 phy_regs_to_save[] = {
		@@ -504,15 +508,17 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
		static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
		B43_PHY_HT_TXPCTL_CMD_C2,
		B43_PHY_HT_TXPCTL_CMD_C3 };
		static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
		B43_PHY_HT_TX_PCTL_STATUS_C2,
		B43_PHY_HT_TX_PCTL_STATUS_C3 };
		int i;

		if (!enable) {
		if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
		/* We disable enabled TX pwr ctl, save it's state */
		/*
		* TODO: find the registers. On N-PHY they were 0x1ed
		* and 0x1ee, we need 3 such a registers for HT-PHY
		*/
		for (i = 0; i < 3; i++)
		phy_ht->tx_pwr_idx[i] =
		b43_phy_read(dev, status_regs[i]);
		}
		b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
		} else {
		@@ -536,13 +542,25 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
		static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
		{
		struct b43_phy_ht *phy_ht = dev->phy.ht;
		static const u16 base[] = { 0x840, 0x860, 0x880 };
		u16 save_regs[3][3];
		s32 rssi_buf[6];
		int core;

		/* TODO */
		for (core = 0; core < 3; core++) {
		save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
		save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
		save_regs[core][0] = b43_phy_read(dev, base[core] + 0);

		b43_phy_write(dev, base[core] + 6, 0);
		b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
		b43_phy_set(dev, base[core] + 0, 0x0400);
		b43_phy_set(dev, base[core] + 0, 0x1000);
		}

		b43_phy_ht_tx_tone(dev);
		udelay(20);
		b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1);
		b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
		b43_phy_ht_stop_playback(dev);
		b43_phy_ht_reset_cca(dev);

		@@ -550,7 +568,23 @@ static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
		phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
		phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;

		/* TODO */
		for (core = 0; core < 3; core++) {
		b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
		b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
		b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
		}
		}

		static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
		{
		static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
		int core;

		/* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
		for (core = 0; core < 3; core++) {
		b43_radio_set(dev, 0x8bf, 0x1);
		b43_radio_write(dev, routing[core] \| 0x0159, 0x0011);
		}
		}

		static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
		@@ -946,6 +980,7 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
		b43_phy_ht_tx_power_ctl(dev, false);
		b43_phy_ht_tx_power_ctl_idle_tssi(dev);
		b43_phy_ht_tx_power_ctl_setup(dev);
		b43_phy_ht_tssi_setup(dev);
		b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);

		return 0;

drivers/net/wireless/b43/phy_ht.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -23,6 +23,9 @@
		#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
		#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
		#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
		#define B43_PHY_HT_EST_PWR_C1 0x118
		#define B43_PHY_HT_EST_PWR_C2 0x119
		#define B43_PHY_HT_EST_PWR_C3 0x11A
		#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
		#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
		#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
		@@ -53,6 +56,8 @@
		#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
		#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
		#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
		#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
		#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
		#define B43_PHY_HT_TXPCTL_CMD_C2 0x222
		#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
		#define B43_PHY_HT_RSSI_C1 0x219
		@@ -97,6 +102,7 @@
		#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
		#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
		#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
		#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)

		#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)

drivers/net/wireless/b43/phy_lp.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -281,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
		} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ \|\|
		(dev->dev->board_type == 0x048A) \|\| ((dev->phy.rev == 0) &&
		(sprom->boardflags_lo & B43_BFL_FEM))) {
		(dev->dev->board_type == SSB_BOARD_BU4312) \|\|
		(dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);

drivers/net/wireless/b43/phy_n.c

+349 −300

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/b43/phy_n.h

+146 −0

Original line number	Diff line number	Diff line
		@@ -54,10 +54,15 @@
		#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
		#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
		#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
		#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
		#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
		#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
		#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
		#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
		#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
		#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
		#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
		#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
		#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
		#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
		#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
		@@ -107,10 +112,15 @@
		#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
		#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
		#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
		#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
		#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
		#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
		#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
		#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
		#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
		#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
		#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
		#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
		#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
		#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
		#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
		@@ -706,10 +716,146 @@
		#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
		#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
		#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
		#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
		#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
		#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
		#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
		#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
		#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
		#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
		#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
		#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
		#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
		#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
		#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
		#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
		#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
		#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
		#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
		#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
		#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
		#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
		#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
		#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
		#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
		#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
		#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
		#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
		#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
		#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
		#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
		/* REV3+ */
		#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
		#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
		#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
		#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
		#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
		#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
		#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
		#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
		#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
		#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
		#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
		#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
		#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
		#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
		#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
		#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
		#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
		#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
		#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
		#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
		#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
		#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
		#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
		#define B43_NPHY_MLUA B43_PHY_N(0x259)
		#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
		#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
		#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
		#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
		#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
		#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
		#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
		#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
		#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
		#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
		#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
		#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
		#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
		#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
		#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
		#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
		#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
		#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
		#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
		#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
		#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
		#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
		#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
		#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
		#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
		#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
		#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
		#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
		#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
		#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
		#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
		#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
		#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
		#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
		#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
		#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
		#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
		#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
		#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
		#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
		#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
		#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
		#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
		#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
		#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
		#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
		#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
		#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
		#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
		#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
		#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
		#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
		#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
		#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
		#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
		#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
		#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
		#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
		#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
		#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
		#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
		#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
		#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
		#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
		#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
		#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
		#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
		#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
		#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
		#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
		#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
		#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
		#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
		#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
		#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
		#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
		#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
		#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
		#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
		#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
		#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
		#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)

		#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
		#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)

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