Commit 278c2cbd authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: merge bit definitions for version 3 ColdFire cache controller 



All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent a12cf0a8

arch/m68k/include/asm/m5307sim.h

+2 −27
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#define	CPU_NAME		"COLDFIRE(m5307)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m53xxacr.h>



/*

 *	Define the 5307 SIM register set addresses.

 */
@@ -160,32 +162,5 @@ 
#define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */

#define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */



/*

 *	Define the Cache register flags.

 */

#define	CACR_EC			(1<<31)

#define	CACR_ESB		(1<<29)

#define	CACR_DPI		(1<<28)

#define	CACR_HLCK		(1<<27)

#define	CACR_CINVA		(1<<24)

#define	CACR_DNFB		(1<<10)

#define	CACR_DCM_WTHRU		(0<<8)

#define	CACR_DCM_WBACK		(1<<8)

#define	CACR_DCM_OFF_PRE	(2<<8)

#define	CACR_DCM_OFF_IMP	(3<<8)

#define	CACR_DW			(1<<5)



#define	ACR_BASE_POS		24

#define	ACR_MASK_POS		16

#define	ACR_ENABLE		(1<<15)

#define	ACR_USER		(0<<13)

#define	ACR_SUPER		(1<<13)

#define	ACR_ANY			(2<<13)

#define	ACR_CM_WTHRU		(0<<5)

#define	ACR_CM_WBACK		(1<<5)

#define	ACR_CM_OFF_PRE		(2<<5)

#define	ACR_CM_OFF_IMP		(3<<5)

#define	ACR_WPROTECT		(1<<2)



/****************************************************************************/

#endif	/* m5307sim_h */

arch/m68k/include/asm/m532xsim.h

+2 −27
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#define	CPU_NAME		"COLDFIRE(m532x)"

#define	CPU_INSTR_PER_JIFFY	3



#include <asm/m53xxacr.h>



#define MCF_REG32(x) (*(volatile unsigned long  *)(x))

#define MCF_REG16(x) (*(volatile unsigned short *)(x))

#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
@@ -76,33 +78,6 @@ 
#define	MCF_IRQ_TIMER		(64 + 32)	/* Timer0 */

#define	MCF_IRQ_PROFILER	(64 + 33)	/* Timer1 */



/*

 *	Define the Cache register flags.

 */

#define	CACR_EC			(1<<31)

#define	CACR_ESB		(1<<29)

#define	CACR_DPI		(1<<28)

#define	CACR_HLCK		(1<<27)

#define	CACR_CINVA		(1<<24)

#define	CACR_DNFB		(1<<10)

#define	CACR_DCM_WTHRU		(0<<8)

#define	CACR_DCM_WBACK		(1<<8)

#define	CACR_DCM_OFF_PRE	(2<<8)

#define	CACR_DCM_OFF_IMP	(3<<8)

#define	CACR_DW			(1<<5)



#define	ACR_BASE_POS		24

#define	ACR_MASK_POS		16

#define	ACR_ENABLE		(1<<15)

#define	ACR_USER		(0<<13)

#define	ACR_SUPER		(1<<13)

#define	ACR_ANY			(2<<13)

#define	ACR_CM_WTHRU		(0<<5)

#define	ACR_CM_WBACK		(1<<5)

#define	ACR_CM_OFF_PRE		(2<<5)

#define	ACR_CM_OFF_IMP		(3<<5)

#define	ACR_WPROTECT		(1<<2)



/*

 *  UART module.

 */

arch/m68k/include/asm/m53xxacr.h

0 → 100644
+52 −0
Original line number Diff line number Diff line 
/****************************************************************************/



/*

 * m53xxacr.h -- ColdFire version 3 core cache support

 *

 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>

 */



/****************************************************************************/

#ifndef m53xxacr_h

#define m53xxacr_h

/****************************************************************************/



/*

 * All varients of the ColdFire using version 3 cores have a similar

 * cache setup. They have a unified instruction and data cache, with

 * configurable write-through or copy-back operation.

 */



/*

 * Define the Cache Control register flags.

 */

#define CACR_EC		0x80000000	/* Enable cache */

#define CACR_ESB	0x20000000	/* Enable store buffer */

#define CACR_DPI	0x10000000	/* Disable invalidation by CPUSHL */

#define CACR_HLCK	0x08000000	/* Half cache lock mode */

#define CACR_CINVA	0x01000000	/* Invalidate cache */

#define CACR_DNFB	0x00000400	/* Inhibited fill buffer */

#define CACR_DCM_WT	0x00000000	/* Cacheable write-through */

#define CACR_DCM_CB	0x00000100	/* Cacheable copy-back */

#define CACR_DCM_PRE	0x00000200	/* Cache inhibited, precise */

#define CACR_DCM_IMPRE	0x00000300	/* Cache inhibited, imprecise */

#define CACR_WPROTECT	0x00000020	/* Write protect*/

#define CACR_EUSP	0x00000010	/* Eanble separate user a7 */



/*

 * Define the Access Control register flags.

 */

#define ACR_BASE_POS	24		/* Address Base (upper 8 bits) */

#define ACR_MASK_POS	16		/* Address Mask (next 8 bits) */

#define ACR_ENABLE	0x00008000	/* Enable this ACR */

#define ACR_USER	0x00000000	/* Allow only user accesses */

#define ACR_SUPER	0x00002000	/* Allow supervisor access only */

#define ACR_ANY		0x00004000	/* Allow any access type */

#define ACR_CM_WT	0x00000000	/* Cacheable, write-through */

#define ACR_CM_CB	0x00000020	/* Cacheable, copy-back */

#define ACR_CM_PRE	0x00000040	/* Cache inhibited, precise */

#define ACR_CM_IMPRE	0x00000060	/* Cache inhibited, imprecise */

#define ACR_WPROTECT	0x00000004	/* Write protect region */



/****************************************************************************/

#endif  /* m53xxsim_h */

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