Commit 275fa0ea authored by Steven Price's avatar Steven Price Committed by Will Deacon
Browse files

arm64: Workaround for Cortex-A55 erratum 1530923 



Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a
result of a speculative AT instruction. This may happen in the middle of
a guest world switch while the relevant VMSA configuration is in an
inconsistent state, leading to erroneous content being allocated into
TLBs.

The same workaround as is used for Cortex-A76 erratum 1165522
(WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this
mandates the use of VHE on affected parts.

Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarSteven Price <steven.price@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent db0d46a5

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -530,6 +530,19 @@ config ARM64_ERRATUM_1165522 


	  If unsure, say Y.



config ARM64_ERRATUM_1530923

	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	help

	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with

	  corrupted TLBs by speculating an AT instruction during a guest

	  context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1286807

	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"

	default y

arch/arm64/include/asm/kvm_hyp.h

+2 −2
Original line number Diff line number Diff line
@@ -91,8 +91,8 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) 
	write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);



	/*

	 * ARM erratum 1165522 requires the actual execution of the above

	 * before we can switch to the EL1/EL0 translation regime used by

	 * ARM errata 1165522 and 1530923 require the actual execution of the

	 * above before we can switch to the EL1/EL0 translation regime used by

	 * the guest.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));

arch/arm64/kernel/cpu_errata.c

+5 −1
Original line number Diff line number Diff line
@@ -762,6 +762,10 @@ static const struct midr_range erratum_speculative_at_vhe_list[] = { 
#ifdef CONFIG_ARM64_ERRATUM_1165522

	/* Cortex A76 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

#endif

#ifdef CONFIG_ARM64_ERRATUM_1530923

	/* Cortex A55 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),

#endif

	{},

};
@@ -895,7 +899,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	{

		.desc = "ARM erratum 1165522",

		.desc = "ARM errata 1165522, 1530923",

		.capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE,

		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list),

	},

arch/arm64/kvm/hyp/switch.c

+2 −2
Original line number Diff line number Diff line
@@ -158,8 +158,8 @@ static void deactivate_traps_vhe(void) 
	write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);



	/*

	 * ARM erratum 1165522 requires the actual execution of the above

	 * before we can switch to the EL2/EL0 translation regime used by

	 * ARM errata 1165522 and 1530923 require the actual execution of the

	 * above before we can switch to the EL2/EL0 translation regime used by

	 * the host.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));

CRA Git | Maintained and supported by SUSTech CRA and CCSE