Commit 275f01b2 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: PCH_ prefix for transcoder timings 



While at it, also extract a common helper to copy the timings from the
cpu transcoder to the pch transcoder. That way it's really explicit
how the lpt transcoder is hardcoded.

v2:
- Re-align #defines properly (Paulo).
- Use cpu_transcoder when copying pipe timings (Paulo).
- s/intel_pch_transcoder_enable/intel_pch_transcoder_set_timings/
  since we already have a pch transcoder enable function, and this is
  clearer, too.
- Fixup 80 char line overflow in intel_display.c. I've opted to ignore
  this in i915_reg.h and i915_ums.c since meh.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ab9412ba

drivers/gpu/drm/i915/i915_reg.h

+35 −35
Original line number Diff line number Diff line
@@ -3929,25 +3929,25 @@ 


/* transcoder */



#define _TRANS_HTOTAL_A          0xe0000

#define _PCH_TRANS_HTOTAL_A		0xe0000

#define  TRANS_HTOTAL_SHIFT		16

#define  TRANS_HACTIVE_SHIFT		0

#define _TRANS_HBLANK_A          0xe0004

#define _PCH_TRANS_HBLANK_A		0xe0004

#define  TRANS_HBLANK_END_SHIFT		16

#define  TRANS_HBLANK_START_SHIFT	0

#define _TRANS_HSYNC_A           0xe0008

#define _PCH_TRANS_HSYNC_A		0xe0008

#define  TRANS_HSYNC_END_SHIFT		16

#define  TRANS_HSYNC_START_SHIFT	0

#define _TRANS_VTOTAL_A          0xe000c

#define _PCH_TRANS_VTOTAL_A		0xe000c

#define  TRANS_VTOTAL_SHIFT		16

#define  TRANS_VACTIVE_SHIFT		0

#define _TRANS_VBLANK_A          0xe0010

#define _PCH_TRANS_VBLANK_A		0xe0010

#define  TRANS_VBLANK_END_SHIFT		16

#define  TRANS_VBLANK_START_SHIFT	0

#define _TRANS_VSYNC_A           0xe0014

#define _PCH_TRANS_VSYNC_A		0xe0014

#define  TRANS_VSYNC_END_SHIFT	 	16

#define  TRANS_VSYNC_START_SHIFT	0

#define _TRANS_VSYNCSHIFT_A	0xe0028

#define _PCH_TRANS_VSYNCSHIFT_A		0xe0028



#define _TRANSA_DATA_M1          0xe0030

#define _TRANSA_DATA_N1          0xe0034
@@ -4025,22 +4025,22 @@ 
#define HSW_TVIDEO_DIP_VSC_DATA(trans) \

	 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)



#define _TRANS_HTOTAL_B          0xe1000

#define _TRANS_HBLANK_B          0xe1004

#define _TRANS_HSYNC_B           0xe1008

#define _TRANS_VTOTAL_B          0xe100c

#define _TRANS_VBLANK_B          0xe1010

#define _TRANS_VSYNC_B           0xe1014

#define _TRANS_VSYNCSHIFT_B	 0xe1028



#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)

#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)

#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)

#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)

#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)

#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)

#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \

				     _TRANS_VSYNCSHIFT_B)

#define _PCH_TRANS_HTOTAL_B          0xe1000

#define _PCH_TRANS_HBLANK_B          0xe1004

#define _PCH_TRANS_HSYNC_B           0xe1008

#define _PCH_TRANS_VTOTAL_B          0xe100c

#define _PCH_TRANS_VBLANK_B          0xe1010

#define _PCH_TRANS_VSYNC_B           0xe1014

#define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028



#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)

#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)

#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)

#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)

#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)

#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)

#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \

					 _PCH_TRANS_VSYNCSHIFT_B)



#define _TRANSB_DATA_M1          0xe1030

#define _TRANSB_DATA_N1          0xe1034

drivers/gpu/drm/i915/i915_ums.c

+24 −24
Original line number Diff line number Diff line
@@ -149,12 +149,12 @@ void i915_save_display_reg(struct drm_device *dev) 
		dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);



		dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);

		dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);

		dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);

		dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);

		dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);

		dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);

		dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);

		dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_PCH_TRANS_HTOTAL_A);

		dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_PCH_TRANS_HBLANK_A);

		dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_PCH_TRANS_HSYNC_A);

		dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_PCH_TRANS_VTOTAL_A);

		dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_PCH_TRANS_VBLANK_A);

		dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_PCH_TRANS_VSYNC_A);

	}



	dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
@@ -206,12 +206,12 @@ void i915_save_display_reg(struct drm_device *dev) 
		dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);



		dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);

		dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);

		dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);

		dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);

		dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);

		dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);

		dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);

		dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_PCH_TRANS_HTOTAL_B);

		dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_PCH_TRANS_HBLANK_B);

		dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_PCH_TRANS_HSYNC_B);

		dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_PCH_TRANS_VTOTAL_B);

		dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_PCH_TRANS_VBLANK_B);

		dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_PCH_TRANS_VSYNC_B);

	}



	dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
@@ -380,12 +380,12 @@ void i915_restore_display_reg(struct drm_device *dev) 
		I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);



		I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);

		I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);

		I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);

		I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);

		I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);

		I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);

		I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);

		I915_WRITE(_PCH_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);

		I915_WRITE(_PCH_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);

		I915_WRITE(_PCH_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);

		I915_WRITE(_PCH_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);

		I915_WRITE(_PCH_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);

		I915_WRITE(_PCH_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);

	}



	/* Restore plane info */
@@ -449,12 +449,12 @@ void i915_restore_display_reg(struct drm_device *dev) 
		I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);



		I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);

		I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);

		I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);

		I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);

		I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);

		I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);

		I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);

		I915_WRITE(_PCH_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);

		I915_WRITE(_PCH_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);

		I915_WRITE(_PCH_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);

		I915_WRITE(_PCH_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);

		I915_WRITE(_PCH_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);

		I915_WRITE(_PCH_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);

	}



	/* Restore plane info */

drivers/gpu/drm/i915/intel_display.c

+26 −16
Original line number Diff line number Diff line
@@ -2995,6 +2995,30 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) 
	mutex_unlock(&dev_priv->dpio_lock);

}



static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,

						enum pipe pch_transcoder)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;



	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),

		   I915_READ(HTOTAL(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),

		   I915_READ(HBLANK(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),

		   I915_READ(HSYNC(cpu_transcoder)));



	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),

		   I915_READ(VTOTAL(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),

		   I915_READ(VBLANK(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),

		   I915_READ(VSYNC(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),

		   I915_READ(VSYNCSHIFT(cpu_transcoder)));

}



/*

 * Enable PCH resources required for PCH ports:

 *   - PCH PLLs
@@ -3058,14 +3082,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 


	/* set transcoder timing, panel must allow it */

	assert_panel_unlocked(dev_priv, pipe);

	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));

	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));

	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));



	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));

	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));

	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));

	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));

	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);



	intel_fdi_normal_train(crtc);
@@ -3120,14 +3137,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) 
	lpt_program_iclkip(crtc);



	/* Set transcoder timing. */

	I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));

	I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));

	I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));



	I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));

	I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));

	I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));

	I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));

	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);



	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);

}

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