KVM: MIPS/VZ: Support guest load-linked bit (273819a6) · Commits · 戴 / test

When restoring guest state after another VCPU has run, be sure to clear CP0_LLAddr.LLB in order to break any interrupted atomic critical section. Without this SMP guest atomics don't work when LLB is present as one guest can complete the atomic section started by another guest. MIPS VZ guest read of CP0_LLAddr causes Guest Privileged Sensitive Instruction (GPSI) exception due to the address being root physical. Handle this by reporting only the LLB bit, which contains the bit for whether a ll/sc atomic is in progress without any reason for failure. Similarly on P5600 a guest write to CP0_LLAddr also causes a GPSI exception. Handle this also by clearing the guest LLB bit from root mode. Signed-off-by:

James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org

arch/mips/kvm/vz.c

+24 −0

Original line number	Diff line number	Diff line
		@@ -730,6 +730,13 @@ static enum emulation_result kvm_vz_gpsi_cop0(union mips_instruction inst,
		} else if (rd == MIPS_CP0_COMPARE &&
		sel == 0) { /* Compare */
		val = read_gc0_compare();
		} else if (rd == MIPS_CP0_LLADDR &&
		sel == 0) { /* LLAddr */
		if (cpu_guest_has_rw_llb)
		val = read_gc0_lladdr() &
		MIPS_LLADDR_LLB;
		else
		val = 0;
		} else if ((rd == MIPS_CP0_PRID &&
		(sel == 0 \|\| /* PRid */
		sel == 2 \|\| /* CDMMBase */
		@@ -777,6 +784,15 @@ static enum emulation_result kvm_vz_gpsi_cop0(union mips_instruction inst,
		kvm_mips_write_compare(vcpu,
		vcpu->arch.gprs[rt],
		true);
		} else if (rd == MIPS_CP0_LLADDR &&
		sel == 0) { /* LLAddr */
		/*
		* P5600 generates GPSI on guest MTC0 LLAddr.
		* Only allow the guest to clear LLB.
		*/
		if (cpu_guest_has_rw_llb &&
		!(val & MIPS_LLADDR_LLB))
		write_gc0_lladdr(0);
		} else if (rd == MIPS_CP0_ERRCTL &&
		(sel == 0)) { /* ErrCtl */
		/* ignore the written value */
		@@ -2247,6 +2263,14 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
		write_c0_guestctl2(
		cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]);

		/*
		* We should clear linked load bit to break interrupted atomics. This
		* prevents a SC on the next VCPU from succeeding by matching a LL on
		* the previous VCPU.
		*/
		if (cpu_guest_has_rw_llb)
		write_gc0_lladdr(0);

		return 0;
		}

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