Commit 2707e444 authored by Zhi Wang's avatar Zhi Wang Committed by Zhenyu Wang
Browse files

drm/i915/gvt: vGPU graphics memory virtualization 



The vGPU graphics memory emulation framework is responsible for graphics
memory table virtualization. Under virtualization environment, a VM will
populate the page table entry with guest page frame number(GPFN/GFN), while
HW needs a page table filled with MFN(Machine frame number). The
relationship between GFN and MFN(Machine frame number) is managed by
hypervisor, while GEN HW doesn't have such knowledge to translate a GFN.

To solve this gap, shadow GGTT/PPGTT page table is introdcued.

For GGTT, the GFN inside the guest GGTT page table entry will be translated
into MFN and written into physical GTT MMIO registers when guest write
virtual GTT MMIO registers.

For PPGTT, a shadow PPGTT page table will be created and write-protected
translated from guest PPGTT page table.  And the shadow page table root
pointers will be written into the shadow context after a guest workload
is shadowed.

vGPU graphics memory emulation framework consists:

- Per-GEN HW platform page table entry bits extract/de-extract routines.
- GTT MMIO register emulation handlers, which will call hypercall to do
GFN->MFN translation when guest write GTT MMIO register
- PPGTT shadow page table routines, e.g. shadow create/destroy/out-of-sync

Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent c8fe6a68

drivers/gpu/drm/i915/gvt/Makefile

+1 −1
Original line number Diff line number Diff line 
GVT_DIR := gvt

GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \

	interrupt.o

	interrupt.o gtt.o



ccflags-y                      += -I$(src) -I$(src)/$(GVT_DIR) -Wall

i915-y			       += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/debug.h

+3 −0
Original line number Diff line number Diff line
@@ -33,4 +33,7 @@ 
#define gvt_dbg_irq(fmt, args...) \

	DRM_DEBUG_DRIVER("gvt: irq: "fmt, ##args)



#define gvt_dbg_mm(fmt, args...) \

	DRM_DEBUG_DRIVER("gvt: mm: "fmt, ##args)



#endif

drivers/gpu/drm/i915/gvt/gtt.c

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+2231 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/gvt/gtt.h

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+270 −0
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 *

 * Authors:

 *    Zhi Wang <zhi.a.wang@intel.com>

 *    Zhenyu Wang <zhenyuw@linux.intel.com>

 *    Xiao Zheng <xiao.zheng@intel.com>

 *

 * Contributors:

 *    Min He <min.he@intel.com>

 *    Bing Niu <bing.niu@intel.com>

 *

 */



#ifndef _GVT_GTT_H_

#define _GVT_GTT_H_



#define GTT_PAGE_SHIFT		12

#define GTT_PAGE_SIZE		(1UL << GTT_PAGE_SHIFT)

#define GTT_PAGE_MASK		(~(GTT_PAGE_SIZE-1))



struct intel_vgpu_mm;



#define INTEL_GVT_GTT_HASH_BITS 8

#define INTEL_GVT_INVALID_ADDR (~0UL)



struct intel_gvt_gtt_entry {

	u64 val64;

	int type;

};



struct intel_gvt_gtt_pte_ops {

	struct intel_gvt_gtt_entry *(*get_entry)(void *pt,

		struct intel_gvt_gtt_entry *e,

		unsigned long index, bool hypervisor_access, unsigned long gpa,

		struct intel_vgpu *vgpu);

	struct intel_gvt_gtt_entry *(*set_entry)(void *pt,

		struct intel_gvt_gtt_entry *e,

		unsigned long index, bool hypervisor_access, unsigned long gpa,

		struct intel_vgpu *vgpu);

	bool (*test_present)(struct intel_gvt_gtt_entry *e);

	void (*clear_present)(struct intel_gvt_gtt_entry *e);

	bool (*test_pse)(struct intel_gvt_gtt_entry *e);

	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);

	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);

};



struct intel_gvt_gtt_gma_ops {

	unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);

	unsigned long (*gma_to_pte_index)(unsigned long gma);

	unsigned long (*gma_to_pde_index)(unsigned long gma);

	unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);

	unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);

	unsigned long (*gma_to_pml4_index)(unsigned long gma);

};



struct intel_gvt_gtt {

	struct intel_gvt_gtt_pte_ops *pte_ops;

	struct intel_gvt_gtt_gma_ops *gma_ops;

	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);

	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);

	struct list_head oos_page_use_list_head;

	struct list_head oos_page_free_list_head;

	struct list_head mm_lru_list_head;

};



enum {

	INTEL_GVT_MM_GGTT = 0,

	INTEL_GVT_MM_PPGTT,

};



struct intel_vgpu_mm {

	int type;

	bool initialized;

	bool shadowed;



	int page_table_entry_type;

	u32 page_table_entry_size;

	u32 page_table_entry_cnt;

	void *virtual_page_table;

	void *shadow_page_table;



	int page_table_level;

	bool has_shadow_page_table;

	u32 pde_base_index;



	struct list_head list;

	struct kref ref;

	atomic_t pincount;

	struct list_head lru_list;

	struct intel_vgpu *vgpu;

};



extern struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(

		struct intel_vgpu_mm *mm,

		void *page_table, struct intel_gvt_gtt_entry *e,

		unsigned long index);



extern struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(

		struct intel_vgpu_mm *mm,

		void *page_table, struct intel_gvt_gtt_entry *e,

		unsigned long index);



#define ggtt_get_guest_entry(mm, e, index) \

	intel_vgpu_mm_get_entry(mm, mm->virtual_page_table, e, index)



#define ggtt_set_guest_entry(mm, e, index) \

	intel_vgpu_mm_set_entry(mm, mm->virtual_page_table, e, index)



#define ggtt_get_shadow_entry(mm, e, index) \

	intel_vgpu_mm_get_entry(mm, mm->shadow_page_table, e, index)



#define ggtt_set_shadow_entry(mm, e, index) \

	intel_vgpu_mm_set_entry(mm, mm->shadow_page_table, e, index)



#define ppgtt_get_guest_root_entry(mm, e, index) \

	intel_vgpu_mm_get_entry(mm, mm->virtual_page_table, e, index)



#define ppgtt_set_guest_root_entry(mm, e, index) \

	intel_vgpu_mm_set_entry(mm, mm->virtual_page_table, e, index)



#define ppgtt_get_shadow_root_entry(mm, e, index) \

	intel_vgpu_mm_get_entry(mm, mm->shadow_page_table, e, index)



#define ppgtt_set_shadow_root_entry(mm, e, index) \

	intel_vgpu_mm_set_entry(mm, mm->shadow_page_table, e, index)



extern struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu,

		int mm_type, void *virtual_page_table, int page_table_level,

		u32 pde_base_index);

extern void intel_vgpu_destroy_mm(struct kref *mm_ref);



struct intel_vgpu_guest_page;



struct intel_vgpu_gtt {

	struct intel_vgpu_mm *ggtt_mm;

	unsigned long active_ppgtt_mm_bitmap;

	struct list_head mm_list_head;

	DECLARE_HASHTABLE(shadow_page_hash_table, INTEL_GVT_GTT_HASH_BITS);

	DECLARE_HASHTABLE(guest_page_hash_table, INTEL_GVT_GTT_HASH_BITS);

	atomic_t n_write_protected_guest_page;

	struct list_head oos_page_list_head;

	struct list_head post_shadow_list_head;

	struct page *scratch_page;

	unsigned long scratch_page_mfn;

};



extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);

extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);



extern int intel_gvt_init_gtt(struct intel_gvt *gvt);

extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);



extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level, void *root_entry);



struct intel_vgpu_oos_page;



struct intel_vgpu_shadow_page {

	void *vaddr;

	struct page *page;

	int type;

	struct hlist_node node;

	unsigned long mfn;

};



struct intel_vgpu_guest_page {

	struct hlist_node node;

	bool writeprotection;

	unsigned long gfn;

	int (*handler)(void *, u64, void *, int);

	void *data;

	unsigned long write_cnt;

	struct intel_vgpu_oos_page *oos_page;

};



struct intel_vgpu_oos_page {

	struct intel_vgpu_guest_page *guest_page;

	struct list_head list;

	struct list_head vm_list;

	int id;

	unsigned char mem[GTT_PAGE_SIZE];

};



#define GTT_ENTRY_NUM_IN_ONE_PAGE 512



struct intel_vgpu_ppgtt_spt {

	struct intel_vgpu_shadow_page shadow_page;

	struct intel_vgpu_guest_page guest_page;

	int guest_page_type;

	atomic_t refcount;

	struct intel_vgpu *vgpu;

	DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);

	struct list_head post_shadow_list;

};



int intel_vgpu_init_guest_page(struct intel_vgpu *vgpu,

		struct intel_vgpu_guest_page *guest_page,

		unsigned long gfn,

		int (*handler)(void *gp, u64, void *, int),

		void *data);



void intel_vgpu_clean_guest_page(struct intel_vgpu *vgpu,

		struct intel_vgpu_guest_page *guest_page);



int intel_vgpu_set_guest_page_writeprotection(struct intel_vgpu *vgpu,

		struct intel_vgpu_guest_page *guest_page);



void intel_vgpu_clear_guest_page_writeprotection(struct intel_vgpu *vgpu,

		struct intel_vgpu_guest_page *guest_page);



struct intel_vgpu_guest_page *intel_vgpu_find_guest_page(

		struct intel_vgpu *vgpu, unsigned long gfn);



int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);



int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);



static inline void intel_gvt_mm_reference(struct intel_vgpu_mm *mm)

{

	kref_get(&mm->ref);

}



static inline void intel_gvt_mm_unreference(struct intel_vgpu_mm *mm)

{

	kref_put(&mm->ref, intel_vgpu_destroy_mm);

}



int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);



void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);



unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,

		unsigned long gma);



struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level, void *root_entry);



int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level);



int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level);



int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu *vgpu,

	unsigned int off, void *p_data, unsigned int bytes);



int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu,

	unsigned int off, void *p_data, unsigned int bytes);



#endif /* _GVT_GTT_H_ */

drivers/gpu/drm/i915/gvt/gvt.c

+10 −0
Original line number Diff line number Diff line
@@ -101,6 +101,9 @@ static void init_device_info(struct intel_gvt *gvt) 
		info->mmio_size = 2 * 1024 * 1024;

		info->mmio_bar = 0;

		info->msi_cap_offset = IS_SKYLAKE(gvt->dev_priv) ? 0xac : 0x90;

		info->gtt_start_offset = 8 * 1024 * 1024;

		info->gtt_entry_size = 8;

		info->gtt_entry_size_shift = 3;

	}

}
@@ -119,6 +122,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv) 
	if (WARN_ON(!gvt->initialized))

		return;



	intel_gvt_clean_gtt(gvt);

	intel_gvt_clean_irq(gvt);

	intel_gvt_clean_mmio_info(gvt);

	intel_gvt_free_firmware(gvt);
@@ -171,10 +175,16 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv) 
	if (ret)

		goto out_free_firmware;



	ret = intel_gvt_init_gtt(gvt);

	if (ret)

		goto out_clean_irq;



	gvt_dbg_core("gvt device creation is done\n");

	gvt->initialized = true;

	return 0;



out_clean_irq:

	intel_gvt_clean_irq(gvt);

out_free_firmware:

	intel_gvt_free_firmware(gvt);

out_clean_mmio_info:

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