Commit 26f64a6b authored by Varsha Rao's avatar Varsha Rao Committed by Greg Kroah-Hartman
Browse files

Staging: vt6655: Replace dwIoBase by iobase 



In this patch dwIoBase is renamed as iobase. This is done to fix the
checkpatch issue of CamelCase.

Signed-off-by: default avatarVarsha Rao <rvarsha016@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 00162ea2

drivers/staging/vt6655/baseband.c

+26 −26
Original line number Diff line number Diff line
@@ -1911,7 +1911,7 @@ void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *      byBBAddr    - address of register in Baseband

 *  Out:

 *      pbyData     - data read
@@ -1922,24 +1922,24 @@ void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, 
bool BBbReadEmbedded(struct vnt_private *priv,

		     unsigned char byBBAddr, unsigned char *pbyData)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	unsigned short ww;

	unsigned char byValue;



	/* BB reg offset */

	VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);

	VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);



	/* turn on REGR */

	MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);

	MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);

	/* W_MAX_TIMEOUT is the timeout period */

	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {

		VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);

		VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);

		if (byValue & BBREGCTL_DONE)

			break;

	}



	/* get BB data */

	VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);

	VNSvInPortB(iobase + MAC_REG_BBREGDATA, pbyData);



	if (ww == W_MAX_TIMEOUT) {

		pr_debug(" DBG_PORT80(0x30)\n");
@@ -1953,7 +1953,7 @@ bool BBbReadEmbedded(struct vnt_private *priv, 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *      byBBAddr    - address of register in Baseband

 *      byData      - data to write

 *  Out:
@@ -1965,20 +1965,20 @@ bool BBbReadEmbedded(struct vnt_private *priv, 
bool BBbWriteEmbedded(struct vnt_private *priv,

		      unsigned char byBBAddr, unsigned char byData)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	unsigned short ww;

	unsigned char byValue;



	/* BB reg offset */

	VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);

	VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);

	/* set BB data */

	VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);

	VNSvOutPortB(iobase + MAC_REG_BBREGDATA, byData);



	/* turn on BBREGCTL_REGW */

	MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);

	MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);

	/* W_MAX_TIMEOUT is the timeout period */

	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {

		VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);

		VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);

		if (byValue & BBREGCTL_DONE)

			break;

	}
@@ -1995,7 +1995,7 @@ bool BBbWriteEmbedded(struct vnt_private *priv, 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *      byRevId     - Revision ID

 *      byRFType    - RF type

 *  Out:
@@ -2009,7 +2009,7 @@ bool BBbVT3253Init(struct vnt_private *priv) 
{

	bool bResult = true;

	int        ii;

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	unsigned char byRFType = priv->byRFType;

	unsigned char byLocalID = priv->byLocalID;
@@ -2031,8 +2031,8 @@ bool BBbVT3253Init(struct vnt_private *priv) 
					byVT3253B0_AGC4_RFMD2959[ii][0],

					byVT3253B0_AGC4_RFMD2959[ii][1]);



			VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);

			MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));

			VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);

			MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));

		}

		priv->abyBBVGA[0] = 0x18;

		priv->abyBBVGA[1] = 0x0A;
@@ -2071,8 +2071,8 @@ bool BBbVT3253Init(struct vnt_private *priv) 
				byVT3253B0_AGC[ii][0],

				byVT3253B0_AGC[ii][1]);



		VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);

		MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));

		VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23);

		MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));



		priv->abyBBVGA[0] = 0x14;

		priv->abyBBVGA[1] = 0x0A;
@@ -2093,7 +2093,7 @@ bool BBbVT3253Init(struct vnt_private *priv) 
		 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)

		 */



		/*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/

		/*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/



		/* Init ANT B select,

		 * RX Config CR10 = 0x28->0x2A,
@@ -2101,7 +2101,7 @@ bool BBbVT3253Init(struct vnt_private *priv) 
		 * make the ANT_A, ANT_B inverted)

		 */



		/*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/

		/*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/

		/* Select VC1/VC2, CR215 = 0x02->0x06 */

		bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
@@ -2149,7 +2149,7 @@ bool BBbVT3253Init(struct vnt_private *priv) 
		priv->ldBmThreshold[2] = 0;

		priv->ldBmThreshold[3] = 0;

		/* Fix VT3226 DFC system timing issue */

		MACvSetRFLE_LatchBase(dwIoBase);

		MACvSetRFLE_LatchBase(iobase);

		/* {{ RobertYu: 20050104 */

	} else if (byRFType == RF_AIROHA7230) {

		for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
@@ -2161,11 +2161,11 @@ bool BBbVT3253Init(struct vnt_private *priv) 
		/* Init ANT B select,TX Config CR09 = 0x61->0x45,

		 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)

		 */

		/*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/

		/*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/

		/* Init ANT B select,RX Config CR10 = 0x28->0x2A,

		 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)

		 */

		/*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/

		/*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/

		/* Select VC1/VC2, CR215 = 0x02->0x06 */

		bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);

		/* }} */
@@ -2253,7 +2253,7 @@ void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData) 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *  Out:

 *      none

 *
@@ -2274,7 +2274,7 @@ BBvSoftwareReset(struct vnt_private *priv) 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *  Out:

 *      none

 *
@@ -2296,7 +2296,7 @@ BBvPowerSaveModeON(struct vnt_private *priv) 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *  Out:

 *      none

 *

drivers/staging/vt6655/card.c

+15 −15
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
 *

 * Revision History:

 *      06-10-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.

 *      08-26-2003 Kyle Hsu:      Modify the defination type of dwIoBase.

 *      08-26-2003 Kyle Hsu:      Modify the defination type of iobase.

 *      09-01-2003 Bryan YC Fan:  Add vUpdateIFS().

 *

 */
@@ -934,20 +934,20 @@ u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2) 
 */

bool CARDbGetCurrentTSF(struct vnt_private *priv, u64 *pqwCurrTSF)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	unsigned short ww;

	unsigned char byData;



	MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TSFCNTRRD);

	MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TSFCNTRRD);

	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {

		VNSvInPortB(dwIoBase + MAC_REG_TFTCTL, &byData);

		VNSvInPortB(iobase + MAC_REG_TFTCTL, &byData);

		if (!(byData & TFTCTL_TSFCNTRRD))

			break;

	}

	if (ww == W_MAX_TIMEOUT)

		return false;

	VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR, (u32 *)pqwCurrTSF);

	VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR + 4, (u32 *)pqwCurrTSF + 1);

	VNSvInPortD(iobase + MAC_REG_TSFCNTR, (u32 *)pqwCurrTSF);

	VNSvInPortD(iobase + MAC_REG_TSFCNTR + 4, (u32 *)pqwCurrTSF + 1);



	return true;

}
@@ -985,7 +985,7 @@ u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval) 
 *

 * Parameters:

 *  In:

 *      dwIoBase        - IO Base

 *      iobase          - IO Base

 *      wBeaconInterval - Beacon Interval

 *  Out:

 *      none
@@ -995,16 +995,16 @@ u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval) 
void CARDvSetFirstNextTBTT(struct vnt_private *priv,

			   unsigned short wBeaconInterval)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	u64 qwNextTBTT = 0;



	CARDbGetCurrentTSF(priv, &qwNextTBTT); /* Get Local TSF counter */



	qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval);

	/* Set NextTBTT */

	VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);

	VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32));

	MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);

	VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);

	VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32));

	MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);

}



/*
@@ -1024,12 +1024,12 @@ void CARDvSetFirstNextTBTT(struct vnt_private *priv, 
void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF,

			 unsigned short wBeaconInterval)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;



	qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval);

	/* Set NextTBTT */

	VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwTSF);

	VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32));

	MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);

	VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwTSF);

	VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32));

	MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);

	pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF);

}

drivers/staging/vt6655/mac.h

+161 −161

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/vt6655/rf.c

+32 −32
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *  Out:

 *      none

 *
@@ -414,16 +414,16 @@ static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { 
 */

static bool s_bAL7230Init(struct vnt_private *priv)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	int     ii;

	bool ret;



	ret = true;



	/* 3-wire control for normal mode */

	VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);

	VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);



	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |

							 SOFTPWRCTL_TXPEINV));

	BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */
@@ -431,7 +431,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) 
		ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]);



	/* PLL On */

	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);



	/* Calibration */

	MACvTimer0MicroSDelay(priv, 150);/* 150us */
@@ -444,7 +444,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) 
	/* TXDCOC:disable, RCK:disable */

	ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]);



	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |

							 SOFTPWRCTL_SWPE2    |

							 SOFTPWRCTL_SWPECTI  |

							 SOFTPWRCTL_TXPEINV));
@@ -453,7 +453,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) 


	/* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */

	/* 3-wire control for power saving mode */

	VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */

	VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */



	return ret;

}
@@ -463,26 +463,26 @@ static bool s_bAL7230Init(struct vnt_private *priv) 
 */

static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	bool ret;



	ret = true;



	/* PLLON Off */

	MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);

	MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);



	ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]);

	ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]);

	ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]);



	/* PLLOn On */

	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);



	/* Set Channel[7] = 0 to tell H/W channel is changing now. */

	VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));

	VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));

	MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL7230);

	/* Set Channel[7] = 1 to tell H/W channel change is done. */

	VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));

	VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));



	return ret;

}
@@ -492,7 +492,7 @@ static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byCha 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *      dwData      - data to write

 *  Out:

 *      none
@@ -502,15 +502,15 @@ static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byCha 
 */

bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	unsigned short ww;

	unsigned long dwValue;



	VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);

	VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);



	/* W_MAX_TIMEOUT is the timeout period */

	for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {

		VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);

		VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue);

		if (dwValue & IFREGCTL_DONE)

			break;

	}
@@ -526,7 +526,7 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *  Out:

 *      none

 *
@@ -535,19 +535,19 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) 
 */

static bool RFbAL2230Init(struct vnt_private *priv)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	int     ii;

	bool ret;



	ret = true;



	/* 3-wire control for normal mode */

	VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);

	VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);



	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI  |

							 SOFTPWRCTL_TXPEINV));

	/* PLL  Off */

	MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);

	MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);



	/* patch abnormal AL2230 frequency output */

	IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
@@ -557,7 +557,7 @@ static bool RFbAL2230Init(struct vnt_private *priv) 
	MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */



	/* PLL On */

	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);



	MACvTimer0MicroSDelay(priv, 150);/* 150us */

	ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
@@ -566,20 +566,20 @@ static bool RFbAL2230Init(struct vnt_private *priv) 
	MACvTimer0MicroSDelay(priv, 30);/* 30us */

	ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);



	MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |

	MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3    |

							 SOFTPWRCTL_SWPE2    |

							 SOFTPWRCTL_SWPECTI  |

							 SOFTPWRCTL_TXPEINV));



	/* 3-wire control for power saving mode */

	VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */

	VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */



	return ret;

}



static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	bool ret;



	ret = true;
@@ -588,10 +588,10 @@ static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byCha 
	ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]);



	/* Set Channel[7] = 0 to tell H/W channel is changing now. */

	VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));

	VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));

	MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230);

	/* Set Channel[7] = 1 to tell H/W channel change is done. */

	VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));

	VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));



	return ret;

}
@@ -676,7 +676,7 @@ bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, 
 *

 * Parameters:

 *  In:

 *      dwIoBase    - I/O base address

 *      iobase      - I/O base address

 *      uChannel    - channel number

 *      bySleepCnt  - SleepProgSyn count

 *
@@ -686,12 +686,12 @@ bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, 
bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType,

			 u16 uChannel)

{

	void __iomem *dwIoBase = priv->PortOffset;

	void __iomem *iobase = priv->PortOffset;

	int   ii;

	unsigned char byInitCount = 0;

	unsigned char bySleepCount = 0;



	VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);

	VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0);

	switch (byRFType) {

	case RF_AIROHA:

	case RF_AL2230S:
@@ -753,7 +753,7 @@ bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, 
 *

 * Parameters:

 *  In:

 *      dwIoBase       - I/O base address

 *      iobase         - I/O base address

 *      dwRFPowerTable - RF Tx Power Setting

 *  Out:

 *      none
@@ -825,7 +825,7 @@ bool RFbSetPower( 
 *

 * Parameters:

 *  In:

 *      dwIoBase       - I/O base address

 *      iobase         - I/O base address

 *      dwRFPowerTable - RF Tx Power Setting

 *  Out:

 *      none

drivers/staging/vt6655/srom.c

+16 −16
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ 
 *

 * Parameters:

 *  In:

 *      dwIoBase        - I/O base address

 *      iobase          - I/O base address

 *      byContntOffset  - address of EEPROM

 *  Out:

 *      none
@@ -68,7 +68,7 @@ 
 * Return Value: data read

 *

 */

unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase,

unsigned char SROMbyReadEmbedded(void __iomem *iobase,

				 unsigned char byContntOffset)

{

	unsigned short wDelay, wNoACK;
@@ -77,18 +77,18 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, 
	unsigned char byOrg;



	byData = 0xFF;

	VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg);

	VNSvInPortB(iobase + MAC_REG_I2MCFG, &byOrg);

	/* turn off hardware retry for getting NACK */

	VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY)));

	VNSvOutPortB(iobase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY)));

	for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) {

		VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID);

		VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset);

		VNSvOutPortB(iobase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID);

		VNSvOutPortB(iobase + MAC_REG_I2MTGAD, byContntOffset);



		/* issue read command */

		VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMR);

		VNSvOutPortB(iobase + MAC_REG_I2MCSR, I2MCSR_EEMR);

		/* wait DONE be set */

		for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) {

			VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait);

			VNSvInPortB(iobase + MAC_REG_I2MCSR, &byWait);

			if (byWait & (I2MCSR_DONE | I2MCSR_NACK))

				break;

			PCAvDelayByIO(CB_DELAY_LOOP_WAIT);
@@ -98,8 +98,8 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, 
			break;

		}

	}

	VNSvInPortB(dwIoBase + MAC_REG_I2MDIPT, &byData);

	VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg);

	VNSvInPortB(iobase + MAC_REG_I2MDIPT, &byData);

	VNSvOutPortB(iobase + MAC_REG_I2MCFG, byOrg);

	return byData;

}
@@ -108,20 +108,20 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, 
 *

 * Parameters:

 *  In:

 *      dwIoBase        - I/O base address

 *      iobase          - I/O base address

 *  Out:

 *      pbyEepromRegs   - EEPROM content Buffer

 *

 * Return Value: none

 *

 */

void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs)

void SROMvReadAllContents(void __iomem *iobase, unsigned char *pbyEepromRegs)

{

	int     ii;



	/* ii = Rom Address */

	for (ii = 0; ii < EEP_MAX_CONTEXT_SIZE; ii++) {

		*pbyEepromRegs = SROMbyReadEmbedded(dwIoBase,

		*pbyEepromRegs = SROMbyReadEmbedded(iobase,

						    (unsigned char)ii);

		pbyEepromRegs++;

	}
@@ -132,21 +132,21 @@ void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs) 
 *

 * Parameters:

 *  In:

 *      dwIoBase        - I/O base address

 *      iobase          - I/O base address

 *  Out:

 *      pbyEtherAddress - Ethernet Address buffer

 *

 * Return Value: none

 *

 */

void SROMvReadEtherAddress(void __iomem *dwIoBase,

void SROMvReadEtherAddress(void __iomem *iobase,

			   unsigned char *pbyEtherAddress)

{

	unsigned char ii;



	/* ii = Rom Address */

	for (ii = 0; ii < ETH_ALEN; ii++) {

		*pbyEtherAddress = SROMbyReadEmbedded(dwIoBase, ii);

		*pbyEtherAddress = SROMbyReadEmbedded(iobase, ii);

		pbyEtherAddress++;

	}

}

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