Commit 26ef5c09 authored by David Gibson's avatar David Gibson Committed by Paul Mackerras
Browse files

[PATCH] powerpc: Merge cacheflush.h and cache.h 



The ppc32 and ppc64 versions of cacheflush.h were almost identical.
The two versions of cache.h are fairly similar, except for a bunch of
register definitions in the ppc32 version which probably belong better
elsewhere.  This patch, therefore, merges both headers.  Notable
points:
	- there are several functions in cacheflush.h which exist only
on ppc32 or only on ppc64.  These are handled by #ifdef for now, but
these should probably be consolidated, along with the actual code
behind them later.
	- Confusingly, both ppc32 and ppc64 have a
flush_dcache_range(), but they're subtly different: it uses dcbf on
ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which
uses dcbf.  These too should be merged and consolidated later.
	- Also flush_dcache_range() was defined in cacheflush.h on
ppc64, and in cache.h on ppc32.  In the merged version it's in
cacheflush.h
	- On ppc32 flush_icache_range() is a normal function from
misc.S.  On ppc64, it was wrapper, testing a feature bit before
calling __flush_icache_range() which does the actual flush.  This
patch takes the ppc64 approach, which amounts to no change on ppc32,
since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean
renaming flush_icache_range() to __flush_icache_range() in
arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S
	- The PReP register info from asm-ppc/cache.h has moved to
arch/ppc/platforms/prep_setup.c
	- The 8xx register info from asm-ppc/cache.h has moved to a
new asm-powerpc/reg_8xx.h, included from reg.h
	- flush_dcache_all() was defined on ppc32 (only), but was
never called (although it was exported).  Thus this patch removes it
from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely.  It's
left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c.

Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP
ARCH=ppc, pmac and CHRP ARCH=powerpc).  Built and booted on POWER5
LPAR (ARCH=powerpc and ARCH=ppc64).

Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc).  Built and
booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64).  Built and booted
on G5 (ARCH=powerpc)

Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent e130bedb

arch/powerpc/kernel/misc_32.S

+1 −22
Original line number Diff line number Diff line
@@ -519,7 +519,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 
 *

 * flush_icache_range(unsigned long start, unsigned long stop)

 */

_GLOBAL(flush_icache_range)

_GLOBAL(__flush_icache_range)

BEGIN_FTR_SECTION

	blr				/* for 601, do nothing */

END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
@@ -607,27 +607,6 @@ _GLOBAL(invalidate_dcache_range) 
	sync				/* wait for dcbi's to get to ram */

	blr



#ifdef CONFIG_NOT_COHERENT_CACHE

/*

 * 40x cores have 8K or 16K dcache and 32 byte line size.

 * 44x has a 32K dcache and 32 byte line size.

 * 8xx has 1, 2, 4, 8K variants.

 * For now, cover the worst case of the 44x.

 * Must be called with external interrupts disabled.

 */

#define CACHE_NWAYS	64

#define CACHE_NLINES	16



_GLOBAL(flush_dcache_all)

	li	r4, (2 * CACHE_NWAYS * CACHE_NLINES)

	mtctr	r4

	lis     r5, KERNELBASE@h

1:	lwz	r3, 0(r5)		/* Load one word from every line */

	addi	r5, r5, L1_CACHE_BYTES

	bdnz    1b

	blr

#endif /* CONFIG_NOT_COHERENT_CACHE */



/*

 * Flush a particular page from the data cache to RAM.

 * Note: this is necessary because the instruction cache does *not*

arch/ppc/kernel/misc.S

+2 −2
Original line number Diff line number Diff line
@@ -497,9 +497,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 
 * and invalidate the corresponding instruction cache blocks.

 * This is a no-op on the 601.

 *

 * flush_icache_range(unsigned long start, unsigned long stop)

 * __flush_icache_range(unsigned long start, unsigned long stop)

 */

_GLOBAL(flush_icache_range)

_GLOBAL(__flush_icache_range)

BEGIN_FTR_SECTION

	blr				/* for 601, do nothing */

END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)

arch/ppc/kernel/ppc_ksyms.c

+1 −0
Original line number Diff line number Diff line
@@ -175,6 +175,7 @@ EXPORT_SYMBOL(pci_bus_to_phys); 
#endif /* CONFIG_PCI */



#ifdef CONFIG_NOT_COHERENT_CACHE

extern void flush_dcache_all(void);

EXPORT_SYMBOL(flush_dcache_all);

#endif

arch/ppc/platforms/prep_setup.c

+9 −0
Original line number Diff line number Diff line
@@ -61,6 +61,15 @@ 
#include <asm/pci-bridge.h>

#include <asm/todc.h>



/* prep registers for L2 */

#define CACHECRBA       0x80000823      /* Cache configuration register address */

#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */

#define L2CACHE_512KB	0x00	/* 512KB */

#define L2CACHE_256KB	0x01	/* 256KB */

#define L2CACHE_1MB	0x02	/* 1MB */

#define L2CACHE_NONE	0x03	/* NONE */

#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */



TODC_ALLOC();



unsigned char ucSystemType;

include/asm-ppc64/cache.h→include/asm-powerpc/cache.h

+40 −0
Original line number Diff line number Diff line 
/*

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; either version

 * 2 of the License, or (at your option) any later version.

 */

#ifndef __ARCH_PPC64_CACHE_H

#define __ARCH_PPC64_CACHE_H

#ifndef _ASM_POWERPC_CACHE_H

#define _ASM_POWERPC_CACHE_H



#include <asm/types.h>

#ifdef __KERNEL__



#include <linux/config.h>



/* bytes per L1 cache line */

#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)

#define L1_CACHE_SHIFT		4

#define MAX_COPY_PREFETCH	1

#elif defined(CONFIG_PPC32)

#define L1_CACHE_SHIFT		5

#define MAX_COPY_PREFETCH	4

#else /* CONFIG_PPC64 */

#define L1_CACHE_SHIFT		7

#endif



#define	L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



#define	SMP_CACHE_BYTES		L1_CACHE_BYTES

#define L1_CACHE_SHIFT_MAX	7 /* largest L1 which this arch supports */



#ifndef __ASSEMBLY__



#if defined(__powerpc64__) && !defined(__ASSEMBLY__)

struct ppc64_caches {

	u32	dsize;			/* L1 d-cache size */

	u32	dline_size;		/* L1 d-cache line size	*/
@@ -30,7 +34,7 @@ struct ppc64_caches { 
};



extern struct ppc64_caches ppc64_caches;

#endif /* __powerpc64__ && ! __ASSEMBLY__ */



#endif



#endif
 
#endif /* __KERNEL__ */

#endif /* _ASM_POWERPC_CACHE_H */

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