Commit 26dca6db authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v5.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:

 "Resource management:

   - Improve resource assignment for hot-added nested bridges, e.g.,
     Thunderbolt (Nicholas Johnson)

  Power management:

   - Optionally print config space of devices before suspend (Chen Yu)

   - Increase D3 delay for AMD Ryzen5/7 XHCI controllers (Daniel Drake)

  Virtualization:

   - Generalize DMA alias quirks (James Sewart)

   - Add DMA alias quirk for PLX PEX NTB (James Sewart)

   - Fix IOV memory leak (Navid Emamdoost)

  AER:

   - Log which device prevents error recovery (Yicong Yang)

  Peer-to-peer DMA:

   - Whitelist Intel SkyLake-E (Armen Baloyan)

  Broadcom iProc host bridge driver:

   - Apply PAXC quirk whether driver is built-in or module (Wei Liu)

  Broadcom STB host bridge driver:

   - Add Broadcom STB PCIe host controller driver (Jim Quinlan)

  Intel Gateway SoC host bridge driver:

   - Add driver for Intel Gateway SoC (Dilip Kota)

  Intel VMD host bridge driver:

   - Add support for DMA aliases on other buses (Jon Derrick)

   - Remove dma_map_ops overrides (Jon Derrick)

   - Remove now-unused X86_DEV_DMA_OPS (Christoph Hellwig)

  NVIDIA Tegra host bridge driver:

   - Fix Tegra30 afi_pex2_ctrl register offset (Marcel Ziswiler)

  Panasonic UniPhier host bridge driver:

   - Remove module code since driver can't be built as a module
     (Masahiro Yamada)

  Qualcomm host bridge driver:

   - Add support for SDM845 PCIe controller (Bjorn Andersson)

  TI Keystone host bridge driver:

   - Fix "num-viewport" DT property error handling (Kishon Vijay Abraham I)

   - Fix link training retries initiation (Yurii Monakov)

   - Fix outbound region mapping (Yurii Monakov)

  Misc:

   - Add Switchtec Gen4 support (Kelvin Cao)

   - Add Switchtec Intercomm Notify and Upstream Error Containment
     support (Logan Gunthorpe)

   - Use dma_set_mask_and_coherent() since Switchtec supports 64-bit
     addressing (Wesley Sheng)"

* tag 'pci-v5.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (60 commits)
  PCI: Allow adjust_bridge_window() to shrink resource if necessary
  PCI: Set resource size directly in adjust_bridge_window()
  PCI: Rename extend_bridge_window() to adjust_bridge_window()
  PCI: Rename extend_bridge_window() parameter
  PCI: Consider alignment of hot-added bridges when assigning resources
  PCI: Remove local variable usage in pci_bus_distribute_available_resources()
  PCI: Pass size + alignment to pci_bus_distribute_available_resources()
  PCI: Rename variables
  PCI: vmd: Add two VMD Device IDs
  PCI: Remove unnecessary braces
  PCI: brcmstb: Add MSI support
  PCI: brcmstb: Add Broadcom STB PCIe host controller driver
  x86/PCI: Remove X86_DEV_DMA_OPS
  PCI: vmd: Remove dma_map_ops overrides
  iommu/vt-d: Remove VMD child device sanity check
  iommu/vt-d: Use pci_real_dma_dev() for mapping
  PCI: Introduce pci_real_dma_dev()
  x86/PCI: Expose VMD's pci_dev in struct pci_sysdata
  x86/PCI: Add to_pci_sysdata() helper
  PCI/AER: Initialize aer_fifo
  ...
parents 846de71b 01b810ed

.mailmap

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com> 
Andreas Herrmann <aherrman@de.ibm.com>

Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>

Andrew Morton <akpm@linux-foundation.org>

Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>

Andrew Murray <amurray@thegoodpenguin.co.uk> <amurray@embedded-bits.co.uk>

Andrew Vasquez <andrew.vasquez@qlogic.com>

Andy Adamson <andros@citi.umich.edu>

Antoine Tenart <antoine.tenart@free-electrons.com>

Documentation/PCI/msi-howto.rst

+1 −1
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@@ -283,5 +283,5 @@ or disabled (0). If 0 is found in any of the msi_bus files belonging 
to bridges between the PCI root and the device, MSIs are disabled.



It is also worth checking the device driver to see whether it supports MSIs.

For example, it may contain calls to pci_irq_alloc_vectors() with the

For example, it may contain calls to pci_alloc_irq_vectors() with the

PCI_IRQ_MSI or PCI_IRQ_MSIX flags.

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Brcmstb PCIe Host Controller Device Tree Bindings



maintainers:

  - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: brcm,bcm2711-pcie # The Raspberry Pi 4



  reg:

    maxItems: 1



  interrupts:

    minItems: 1

    maxItems: 2

    items:

      - description: PCIe host controller

      - description: builtin MSI controller



  interrupt-names:

    minItems: 1

    maxItems: 2

    items:

      - const: pcie

      - const: msi



  ranges:

    maxItems: 1



  dma-ranges:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: sw_pcie



  msi-controller:

    description: Identifies the node as an MSI controller.



  msi-parent:

    description: MSI controller the device is capable of using.



  brcm,enable-ssc:

    description: Indicates usage of spread-spectrum clocking.

    type: boolean



required:

  - reg

  - dma-ranges

  - "#interrupt-cells"

  - interrupts

  - interrupt-names

  - interrupt-map-mask

  - interrupt-map

  - msi-controller



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    scb {

            #address-cells = <2>;

            #size-cells = <1>;

            pcie0: pcie@7d500000 {

                    compatible = "brcm,bcm2711-pcie";

                    reg = <0x0 0x7d500000 0x9310>;

                    device_type = "pci";

                    #address-cells = <3>;

                    #size-cells = <2>;

                    #interrupt-cells = <1>;

                    interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

                                 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

                    interrupt-names = "pcie", "msi";

                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;

                    interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

                    msi-parent = <&pcie0>;

                    msi-controller;

                    ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;

                    dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;

                    brcm,enable-ssc;

            };

    };

Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PCIe RC controller on Intel Gateway SoCs



maintainers:

  - Dilip Kota <eswara.kota@linux.intel.com>



properties:

  compatible:

    items:

      - const: intel,lgm-pcie

      - const: snps,dw-pcie



  device_type:

    const: pci



  "#address-cells":

    const: 3



  "#size-cells":

    const: 2



  reg:

    items:

      - description: Controller control and status registers.

      - description: PCIe configuration registers.

      - description: Controller application registers.



  reg-names:

    items:

      - const: dbi

      - const: config

      - const: app



  ranges:

    maxItems: 1



  resets:

    maxItems: 1



  clocks:

    maxItems: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie



  reset-gpios:

    maxItems: 1



  linux,pci-domain: true



  num-lanes:

    maximum: 2

    description: Number of lanes to use for this port.



  '#interrupt-cells':

    const: 1



  interrupt-map-mask:

    description: Standard PCI IRQ mapping properties.



  interrupt-map:

    description: Standard PCI IRQ mapping properties.



  max-link-speed:

    description: Specify PCI Gen for link capability.

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

      - enum: [ 1, 2, 3, 4 ]

      - default: 1



  bus-range:

    description: Range of bus numbers associated with this controller.



  reset-assert-ms:

    description: |

      Delay after asserting reset to the PCIe device.

    maximum: 500

    default: 100



required:

  - compatible

  - device_type

  - "#address-cells"

  - "#size-cells"

  - reg

  - reg-names

  - ranges

  - resets

  - clocks

  - phys

  - phy-names

  - reset-gpios

  - '#interrupt-cells'

  - interrupt-map

  - interrupt-map-mask



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/clock/intel,lgm-clk.h>

    pcie10: pcie@d0e00000 {

      compatible = "intel,lgm-pcie", "snps,dw-pcie";

      device_type = "pci";

      #address-cells = <3>;

      #size-cells = <2>;

      reg = <0xd0e00000 0x1000>,

            <0xd2000000 0x800000>,

            <0xd0a41000 0x1000>;

      reg-names = "dbi", "config", "app";

      linux,pci-domain = <0>;

      max-link-speed = <4>;

      bus-range = <0x00 0x08>;

      interrupt-parent = <&ioapic1>;

      #interrupt-cells = <1>;

      interrupt-map-mask = <0 0 0 0x7>;

      interrupt-map = <0 0 0 1 &ioapic1 27 1>,

                      <0 0 0 2 &ioapic1 28 1>,

                      <0 0 0 3 &ioapic1 29 1>,

                      <0 0 0 4 &ioapic1 30 1>;

      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;

      resets = <&rcu0 0x50 0>;

      clocks = <&cgu0 LGM_GCLK_PCIE10>;

      phys = <&cb0phy0>;

      phy-names = "pcie";

      reset-assert-ms = <500>;

      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;

      num-lanes = <2>;

    };

Documentation/devicetree/bindings/pci/qcom,pcie.txt

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@@ -11,6 +11,7 @@ 
			- "qcom,pcie-ipq4019" for ipq4019

			- "qcom,pcie-ipq8074" for ipq8074

			- "qcom,pcie-qcs404" for qcs404

			- "qcom,pcie-sdm845" for sdm845



- reg:

	Usage: required
@@ -126,6 +127,18 @@ 
			- "master_bus"	AXI Master clock

			- "slave_bus"	AXI Slave clock



-clock-names:

	Usage: required for sdm845

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary clock

			- "cfg"		Configuration clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock

			- "slave_q2a"	Slave Q2A clock

			- "tbu"		PCIe TBU clock

			- "pipe"	PIPE clock



- resets:

	Usage: required

	Value type: <prop-encoded-array>
@@ -188,6 +201,12 @@ 
			- "pwr"			PWR reset

			- "ahb"			AHB reset



- reset-names:

	Usage: required for sdm845

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pci"			PCIe core reset



- power-domains:

	Usage: required for apq8084 and msm8996/apq8096

	Value type: <prop-encoded-array>

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