PCI quirk: unhide 'Overflow' device on i828{6,7}5P/PE chipsets (26c56dc0) · Commits · 戴 / test

Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by:

Michal Miroslaw <mirq-linux@rere.qmqm.pl> Acked-by:

Doug Thompson <norsk5@yahoo.com> Signed-off-by:

Andrew Morton <akpm@linux-foundation.org> Signed-off-by:

Jesse Barnes <jbarnes@virtuousgeek.org>

drivers/pci/quirks.c

+22 −0

Original line number	Diff line number	Diff line
		@@ -2017,6 +2017,28 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
		PCI_DEVICE_ID_NX2_5709S,
		quirk_brcm_570x_limit_vpd);

		/* Originally in EDAC sources for i82875P:
		* Intel tells BIOS developers to hide device 6 which
		* configures the overflow device access containing
		* the DRBs - this is where we expose device 6.
		* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
		*/
		static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
		{
		u8 reg;

		if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
		dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
		pci_write_config_byte(dev, 0xF4, reg \| 0x02);
		}
		}

		DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
		quirk_unhide_mch_dev6);
		DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
		quirk_unhide_mch_dev6);


		#ifdef CONFIG_PCI_MSI
		/* Some chipsets do not support MSI. We cannot easily rely on setting
		* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually

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