Commit 26b99db0 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.17' of... 

Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

Our usual bunch of changes for the next merge window. The most significant
addition is the support of the H6 clock unit. Other than that, there's a
bunch of fixes for the video clocks on the H3 and H5, and some Kconfig
cleanup.

* tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
  clk: sunxi-ng: add support for the Allwinner H6 CCU
  dt-bindings: add device tree binding for Allwinner H6 main CCU
  clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
  clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
  clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
  clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
  clk: sunxi-ng: Add check for minimal rate to NM PLLs
  clk: sunxi-ng: Use u64 for calculation of nkmp rate
  clk: sunxi-ng: Mask nkmp factors when setting register
  clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
parents 7928b2cb f422fa55

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ Required properties : 
		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"

		- "allwinner,sun50i-h6-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length
@@ -31,6 +32,9 @@ Required properties : 
- #clock-cells : must contain 1

- #reset-cells : must contain 1



For the main CCU on H6, one more clock is needed:

- "iosc": the SoC's internal frequency oscillator



For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator

drivers/clk/sunxi-ng/Kconfig

+5 −7
Original line number Diff line number Diff line
@@ -11,15 +11,13 @@ config SUN50I_A64_CCU 
	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_H6_CCU

	bool "Support for the Allwinner H6 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN4I_A10_CCU

	bool "Support for the Allwinner A10/A20 CCU"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_MULT

	select SUNXI_CCU_NK

	select SUNXI_CCU_NKM

	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN4I

	default MACH_SUN7I

	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o 


# SoC support

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o

obj-$(CONFIG_SUN4I_A10_CCU)	+= ccu-sun4i-a10.o

obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o

obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

0 → 100644
+1211 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun50i-h6.h

0 → 100644
+56 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright 2016 Icenowy Zheng <icenowy@aosc.io>

 */



#ifndef _CCU_SUN50I_H6_H_

#define _CCU_SUN50I_H6_H_



#include <dt-bindings/clock/sun50i-h6-ccu.h>

#include <dt-bindings/reset/sun50i-h6-ccu.h>



#define CLK_OSC12M		0

#define CLK_PLL_CPUX		1

#define CLK_PLL_DDR0		2



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X	4

#define CLK_PLL_PERIPH0_4X	5

#define CLK_PLL_PERIPH1		6

#define CLK_PLL_PERIPH1_2X	7

#define CLK_PLL_PERIPH1_4X	8

#define CLK_PLL_GPU		9

#define CLK_PLL_VIDEO0		10

#define CLK_PLL_VIDEO0_4X	11

#define CLK_PLL_VIDEO1		12

#define CLK_PLL_VIDEO1_4X	13

#define CLK_PLL_VE		14

#define CLK_PLL_DE		15

#define CLK_PLL_HSIC		16

#define CLK_PLL_AUDIO_BASE	17

#define CLK_PLL_AUDIO		18

#define CLK_PLL_AUDIO_2X	19

#define CLK_PLL_AUDIO_4X	20



/* CPUX clock exported for DVFS */



#define CLK_AXI			22

#define CLK_CPUX_APB		23

#define CLK_PSI_AHB1_AHB2	24

#define CLK_AHB3		25



/* APB1 clock exported for PIO */



#define CLK_APB2		27

#define CLK_MBUS		28



/* All module clocks and bus gates are exported except DRAM */



#define CLK_DRAM		52



#define CLK_BUS_DRAM		60



#define CLK_NUMBER		(CLK_BUS_HDCP + 1)



#endif /* _CCU_SUN50I_H6_H_ */

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