arm64: remove broken cachepolicy code (26a945ca) · Commits · 戴 / test

The cachepolicy kernel parameter was intended to aid in the debugging of coherency issues, but it is fundamentally broken for several reasons: * On SMP platforms, only the boot CPU's tcr_el1 is altered. Secondary CPUs may therefore use differ w.r.t. the attributes they apply to MT_NORMAL memory, resulting in a loss of coherency. * The cache maintenance using flush_dcache_all (based on Set/Way operations) is not guaranteed to empty a given CPU's cache hierarchy while said CPU has caches enabled, it cannot empty the caches of other coherent PEs, nor is it guaranteed to flush data to the PoC even when caches are disabled. * The TLBs are not invalidated around the modification of MAIR_EL1 and TCR_EL1, as required by the architecture (as both are permitted to be cached in a TLB). This may result in CPUs using attributes other than those expected for some memory accesses, resulting in a loss of coherency. * Exclusive accesses are not architecturally guaranteed to function as expected on memory marked as Write-Through or Non-Cacheable. Thus changing the attributes of MT_NORMAL away from the (architecurally safe) defaults may cause uses of these instructions (e.g. atomics) to behave erratically. Given this, the cachepolicy code cannot be used for debugging purposes as it alone is likely to cause coherency issues. This patch removes the broken cachepolicy code. Signed-off-by:

Mark Rutland <mark.rutland@arm.com> Acked-by:

Will Deacon <will.deacon@arm.com> Signed-off-by:

Catalin Marinas <catalin.marinas@arm.com>

arch/arm64/mm/mmu.c

+0 −74

Original line number	Diff line number	Diff line
		@@ -45,80 +45,6 @@
		struct page *empty_zero_page;
		EXPORT_SYMBOL(empty_zero_page);

		struct cachepolicy {
		const char policy[16];
		u64 mair;
		u64 tcr;
		};

		static struct cachepolicy cache_policies[] __initdata = {
		{
		.policy = "uncached",
		.mair = 0x44, /* inner, outer non-cacheable */
		.tcr = TCR_IRGN_NC \| TCR_ORGN_NC,
		}, {
		.policy = "writethrough",
		.mair = 0xaa, /* inner, outer write-through, read-allocate */
		.tcr = TCR_IRGN_WT \| TCR_ORGN_WT,
		}, {
		.policy = "writeback",
		.mair = 0xee, /* inner, outer write-back, read-allocate */
		.tcr = TCR_IRGN_WBnWA \| TCR_ORGN_WBnWA,
		}
		};

		/*
		* These are useful for identifying cache coherency problems by allowing the
		* cache or the cache and writebuffer to be turned off. It changes the Normal
		* memory caching attributes in the MAIR_EL1 register.
		*/
		static int __init early_cachepolicy(char *p)
		{
		int i;
		u64 tmp;

		for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
		int len = strlen(cache_policies[i].policy);

		if (memcmp(p, cache_policies[i].policy, len) == 0)
		break;
		}
		if (i == ARRAY_SIZE(cache_policies)) {
		pr_err("ERROR: unknown or unsupported cache policy: %s\n", p);
		return 0;
		}

		flush_cache_all();

		/*
		* Modify MT_NORMAL attributes in MAIR_EL1.
		*/
		asm volatile(
		" mrs %0, mair_el1\n"
		" bfi %0, %1, %2, #8\n"
		" msr mair_el1, %0\n"
		" isb\n"
		: "=&r" (tmp)
		: "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8));

		/*
		* Modify TCR PTW cacheability attributes.
		*/
		asm volatile(
		" mrs %0, tcr_el1\n"
		" bic %0, %0, %2\n"
		" orr %0, %0, %1\n"
		" msr tcr_el1, %0\n"
		" isb\n"
		: "=&r" (tmp)
		: "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK \| TCR_ORGN_MASK));

		flush_cache_all();

		return 0;
		}
		early_param("cachepolicy", early_cachepolicy);

		pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
		unsigned long size, pgprot_t vma_prot)
		{

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