Commit 268aebaa authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: allow varying mux parameters for cpuclk pll-sources 



Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9387bfd1

drivers/clk/rockchip/clk-cpu.c

+18 −11
Original line number Diff line number Diff line
@@ -158,11 +158,15 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, 


		writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,

					      reg_data->div_core_shift) |

		       HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),

		       HIWORD_UPDATE(reg_data->mux_core_alt,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),

		       cpuclk->reg_base + reg_data->core_reg);

	} else {

		/* select alternate parent */

		writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),

		writel(HIWORD_UPDATE(reg_data->mux_core_alt,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),

		       cpuclk->reg_base + reg_data->core_reg);

	}
@@ -198,7 +202,9 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, 


	writel(HIWORD_UPDATE(0, reg_data->div_core_mask,

				reg_data->div_core_shift) |

	       HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),

	       HIWORD_UPDATE(reg_data->mux_core_main,

				reg_data->mux_core_mask,

				reg_data->mux_core_shift),

	       cpuclk->reg_base + reg_data->core_reg);



	if (ndata->old_rate > ndata->new_rate)
@@ -252,7 +258,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 
		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.parent_names = &parent_names[0];

	init.parent_names = &parent_names[reg_data->mux_core_main];

	init.num_parents = 1;

	init.ops = &rockchip_cpuclk_ops;
@@ -270,10 +276,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 
	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;

	cpuclk->hw.init = &init;



	cpuclk->alt_parent = __clk_lookup(parent_names[1]);

	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);

	if (!cpuclk->alt_parent) {

		pr_err("%s: could not lookup alternate parent\n",

		       __func__);

		pr_err("%s: could not lookup alternate parent: (%d)\n",

		       __func__, reg_data->mux_core_alt);

		ret = -EINVAL;

		goto free_cpuclk;

	}
@@ -285,10 +291,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 
		goto free_cpuclk;

	}



	clk = __clk_lookup(parent_names[0]);

	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);

	if (!clk) {

		pr_err("%s: could not lookup parent clock %s\n",

		       __func__, parent_names[0]);

		pr_err("%s: could not lookup parent clock: (%d) %s\n",

		       __func__, reg_data->mux_core_main,

		       parent_names[reg_data->mux_core_main]);

		ret = -EINVAL;

		goto free_alt_parent;

	}

drivers/clk/rockchip/clk-rk3036.c

+3 −0
Original line number Diff line number Diff line
@@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { 
	.core_reg = RK2928_CLKSEL_CON(0),

	.div_core_shift = 0,

	.div_core_mask = 0x1f,

	.mux_core_alt = 1,

	.mux_core_main = 0,

	.mux_core_shift = 7,

	.mux_core_mask = 0x1,

};



PNAME(mux_pll_p)		= { "xin24m", "xin24m" };

drivers/clk/rockchip/clk-rk3188.c

+6 −0
Original line number Diff line number Diff line
@@ -155,7 +155,10 @@ static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { 
	.core_reg = RK2928_CLKSEL_CON(0),

	.div_core_shift = 0,

	.div_core_mask = 0x1f,

	.mux_core_alt = 1,

	.mux_core_main = 0,

	.mux_core_shift = 8,

	.mux_core_mask = 0x1,

};



#define RK3188_DIV_ACLK_CORE_MASK	0x7
@@ -191,7 +194,10 @@ static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { 
	.core_reg = RK2928_CLKSEL_CON(0),

	.div_core_shift = 9,

	.div_core_mask = 0x1f,

	.mux_core_alt = 1,

	.mux_core_main = 0,

	.mux_core_shift = 8,

	.mux_core_mask = 0x1,

};



PNAME(mux_pll_p)		= { "xin24m", "xin32k" };

drivers/clk/rockchip/clk-rk3228.c

+3 −0
Original line number Diff line number Diff line
@@ -111,7 +111,10 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { 
	.core_reg = RK2928_CLKSEL_CON(0),

	.div_core_shift = 0,

	.div_core_mask = 0x1f,

	.mux_core_alt = 1,

	.mux_core_main = 0,

	.mux_core_shift = 6,

	.mux_core_mask = 0x1,

};



PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };

drivers/clk/rockchip/clk-rk3288.c

+3 −0
Original line number Diff line number Diff line
@@ -165,7 +165,10 @@ static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { 
	.core_reg = RK3288_CLKSEL_CON(0),

	.div_core_shift = 8,

	.div_core_mask = 0x1f,

	.mux_core_alt = 1,

	.mux_core_main = 0,

	.mux_core_shift = 15,

	.mux_core_mask = 0x1,

};



PNAME(mux_pll_p)		= { "xin24m", "xin32k" };

CRA Git | Maintained and supported by SUSTech CRA and CCSE