Unverified Commit 268a2d60 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Paul Burton
Browse files

MIPS: Loongson64: Rename CPU TYPES 



CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64

As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while 2E/2F are less similar with
other LOONGSON64 products.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarPaul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
parent 2409839a

arch/mips/Kconfig

+18 −18
Original line number Diff line number Diff line
@@ -1377,9 +1377,9 @@ choice 
	prompt "CPU type"

	default CPU_R4X00



config CPU_LOONGSON3

	bool "Loongson 3 CPU"

	depends on SYS_HAS_CPU_LOONGSON3

config CPU_LOONGSON64

	bool "Loongson GSx64 CPU"

	depends on SYS_HAS_CPU_LOONGSON64

	select ARCH_HAS_PHYS_TO_DMA

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1394,19 +1394,19 @@ config CPU_LOONGSON3 
	select GPIOLIB

	select SWIOTLB

	help

		The Loongson 3 processor implements the MIPS64R2 instruction

		set with many extensions.

		The Loongson GSx64 series of processor cores implements the

		MIPS64R2 instruction set with many extensions.



config LOONGSON3_ENHANCEMENT

	bool "New Loongson 3 CPU Enhancements"

config LOONGSON64_ENHANCEMENT

	bool "New Loongson GSx64E CPU Enhancements"

	default n

	select CPU_MIPSR2

	select CPU_HAS_PREFETCH

	depends on CPU_LOONGSON3

	depends on CPU_LOONGSON64

	help

	  New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A

	  New Loongson GSx64E cores (since Loongson-3A R2, as opposed to Loongson-3A

	  R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as

	  FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User

	  FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User

	  Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),

	  Fast TLB refill support, etc.
@@ -1418,7 +1418,7 @@ config LOONGSON3_ENHANCEMENT 
config CPU_LOONGSON3_WORKAROUNDS

	bool "Old Loongson 3 LLSC Workarounds"

	default y if SMP

	depends on CPU_LOONGSON3

	depends on CPU_LOONGSON64

	help

	  Loongson 3 processors have the llsc issues which require workarounds.

	  Without workarounds the system may hang unexpectedly.
@@ -1433,7 +1433,7 @@ config CPU_LOONGSON3_WORKAROUNDS 
config CPU_LOONGSON2E

	bool "Loongson 2E"

	depends on SYS_HAS_CPU_LOONGSON2E

	select CPU_LOONGSON2

	select CPU_LOONGSON2EF

	help

	  The Loongson 2E processor implements the MIPS III instruction set

	  with many extensions.
@@ -1444,7 +1444,7 @@ config CPU_LOONGSON2E 
config CPU_LOONGSON2F

	bool "Loongson 2F"

	depends on SYS_HAS_CPU_LOONGSON2F

	select CPU_LOONGSON2

	select CPU_LOONGSON2EF

	select GPIOLIB

	help

	  The Loongson 2F processor implements the MIPS III instruction set
@@ -1857,7 +1857,7 @@ config SYS_SUPPORTS_ZBOOT_UART_PROM 
	bool

	select SYS_SUPPORTS_ZBOOT



config CPU_LOONGSON2

config CPU_LOONGSON2EF

	bool

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL
@@ -1900,7 +1900,7 @@ config CPU_BMIPS5000 
	select SYS_SUPPORTS_HOTPLUG_CPU

	select CPU_HAS_RIXI



config SYS_HAS_CPU_LOONGSON3

config SYS_HAS_CPU_LOONGSON64

	bool

	select CPU_SUPPORTS_CPUFREQ

	select CPU_HAS_RIXI
@@ -2162,7 +2162,7 @@ choice 


config PAGE_SIZE_4KB

	bool "4kB"

	depends on !CPU_LOONGSON2 && !CPU_LOONGSON3

	depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64

	help

	  This option select the standard 4kB Linux page size.  On some

	  R3000-family processors this is the only available page size.  Using
@@ -2616,7 +2616,7 @@ config CPU_SUPPORTS_MSA 


config ARCH_FLATMEM_ENABLE

	def_bool y

	depends on !NUMA && !CPU_LOONGSON2

	depends on !NUMA && !CPU_LOONGSON2EF



config ARCH_SPARSEMEM_ENABLE

	bool
@@ -2697,7 +2697,7 @@ config NODES_SHIFT 


config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)

	depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)

	default y

	help

	  Enable hardware performance counter support for perf events. If

arch/mips/include/asm/cop2.h

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *); 
#define cop2_present		1

#define cop2_lazy_restore	0



#elif defined(CONFIG_CPU_LOONGSON3)

#elif defined(CONFIG_CPU_LOONGSON64)



#define cop2_present		1

#define cop2_lazy_restore	1

arch/mips/include/asm/cpu-type.h

+4 −5
Original line number Diff line number Diff line
@@ -15,13 +15,12 @@ 
static inline int __pure __get_cpu_type(const int cpu_type)

{

	switch (cpu_type) {

#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \

    defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)

	case CPU_LOONGSON2:

#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2EF)

	case CPU_LOONGSON2EF:

#endif



#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3

	case CPU_LOONGSON3:

#ifdef CONFIG_SYS_HAS_CPU_LOONGSON64

	case CPU_LOONGSON64:

#endif



#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \

arch/mips/include/asm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -319,8 +319,8 @@ enum cpu_type_enum { 
	/*

	 * MIPS64 class processors

	 */

	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,

	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,

	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,

	CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,

	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,



	CPU_QEMU_GENERIC,

arch/mips/include/asm/hazards.h

+2 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
 * TLB hazards

 */

#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \

	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)

	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON64_ENHANCEMENT)



/*

 * MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do { \ 
} while (0)



#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \

	defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \

	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON64_ENHANCEMENT) || \

	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)



/*

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