Commit 2686e07b authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
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ASoC: McBSP: get hw params from McBSP driver 



Removed the use of macros to obtain base address and DMA channel number.
Instead use the McBSP driver API's that passes base address and DMA
channel number to the client driver.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Acked-by: default avatarPeter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: default avatarJarkko Nikula <jhnikula@gmail.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 9504ba64

sound/soc/omap/omap-mcbsp.c

+4 −122
Original line number Diff line number Diff line
@@ -69,110 +69,6 @@ static struct omap_mcbsp_data mcbsp_data[NUM_LINKS]; 
 */

static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];



#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)

static const int omap1_dma_reqs[][2] = {

	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },

	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },

	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },

};

static const unsigned long omap1_mcbsp_port[][2] = {

	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,

	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },

	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,

	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },

	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,

	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },

};

#else

static const int omap1_dma_reqs[][2] = {};

static const unsigned long omap1_mcbsp_port[][2] = {};

#endif



#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)

static const int omap24xx_dma_reqs[][2] = {

	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },

	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },

#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3)

	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },

	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },

	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },

#endif

};

#else

static const int omap24xx_dma_reqs[][2] = {};

#endif



#if defined(CONFIG_ARCH_OMAP4)

static const int omap44xx_dma_reqs[][2] = {

	{ OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },

	{ OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },

	{ OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },

	{ OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },

};

#else

static const int omap44xx_dma_reqs[][2] = {};

#endif



#if defined(CONFIG_SOC_OMAP2420)

static const unsigned long omap2420_mcbsp_port[][2] = {

	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,

	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },

	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,

	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },

};

#else

static const unsigned long omap2420_mcbsp_port[][2] = {};

#endif



#if defined(CONFIG_SOC_OMAP2430)

static const unsigned long omap2430_mcbsp_port[][2] = {

	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },

};

#else

static const unsigned long omap2430_mcbsp_port[][2] = {};

#endif



#if defined(CONFIG_ARCH_OMAP3)

static const unsigned long omap34xx_mcbsp_port[][2] = {

	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },

};

#else

static const unsigned long omap34xx_mcbsp_port[][2] = {};

#endif



#if defined(CONFIG_ARCH_OMAP4)

static const unsigned long omap44xx_mcbsp_port[][2] = {

	{ OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },

	{ OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,

	  OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },

};

#else

static const unsigned long omap44xx_mcbsp_port[][2] = {};

#endif



static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)

{

	struct snd_soc_pcm_runtime *rtd = substream->private_data;
@@ -346,24 +242,10 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 
	unsigned int format, div, framesize, master;



	dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];

	if (cpu_class_is_omap1()) {

		dma = omap1_dma_reqs[bus_id][substream->stream];

		port = omap1_mcbsp_port[bus_id][substream->stream];

	} else if (cpu_is_omap2420()) {

		dma = omap24xx_dma_reqs[bus_id][substream->stream];

		port = omap2420_mcbsp_port[bus_id][substream->stream];

	} else if (cpu_is_omap2430()) {

		dma = omap24xx_dma_reqs[bus_id][substream->stream];

		port = omap2430_mcbsp_port[bus_id][substream->stream];

	} else if (cpu_is_omap343x()) {

		dma = omap24xx_dma_reqs[bus_id][substream->stream];

		port = omap34xx_mcbsp_port[bus_id][substream->stream];

	 } else if (cpu_is_omap44xx()) {

		dma = omap44xx_dma_reqs[bus_id][substream->stream];

		port = omap44xx_mcbsp_port[bus_id][substream->stream];

	} else {

		return -ENODEV;

	}



	dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream);

	port = omap_mcbsp_dma_reg_params(bus_id, substream->stream);



	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:

		dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;

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