Commit 2648298a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_fixes_for_v5.8_v2' of... 

Merge tag 'socfpga_fixes_for_v5.8_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixes

arm/arm64: dts: socfpga: fixes for v5.8
- Add status = "okay" in QSPI
- Increase QSPI size in reg property
- Fix dtschema for SoCFPGA platforms

* tag 'socfpga_fixes_for_v5.8_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema
  ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
  arm64: dts: stratix10: increase QSPI reg address in nand dts file
  arm64: dts: stratix10: add status to qspi dts node
  arm64: dts: agilex: add status to qspi dts node

Link: https://lore.kernel.org/r/20200717155758.18233-1-dinguyen@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f7d96b86 681a5c71

arch/arm/boot/dts/socfpga.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -726,7 +726,7 @@ 
			};

		};



		L2: l2-cache@fffef000 {

		L2: cache-controller@fffef000 {

			compatible = "arm,pl310-cache";

			reg = <0xfffef000 0x1000>;

			interrupts = <0 38 0x04>;

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -636,7 +636,7 @@ 
			reg = <0xffcfb100 0x80>;

		};



		L2: l2-cache@fffff000 {

		L2: cache-controller@fffff000 {

			compatible = "arm,pl310-cache";

			reg = <0xfffff000 0x1000>;

			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ 
		method = "smc";

	};



	intc: intc@fffc1000 {

	intc: interrupt-controller@fffc1000 {

		compatible = "arm,gic-400", "arm,cortex-a15-gic";

		#interrupt-cells = <3>;

		interrupt-controller;
@@ -302,7 +302,7 @@ 
			status = "disabled";

		};



		nand: nand@ffb90000 {

		nand: nand-controller@ffb90000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "altr,socfpga-denali-nand";
@@ -445,7 +445,7 @@ 
			clock-names = "timer";

		};



		uart0: serial0@ffc02000 {

		uart0: serial@ffc02000 {

			compatible = "snps,dw-apb-uart";

			reg = <0xffc02000 0x100>;

			interrupts = <0 108 4>;
@@ -456,7 +456,7 @@ 
			status = "disabled";

		};



		uart1: serial1@ffc02100 {

		uart1: serial@ffc02100 {

			compatible = "snps,dw-apb-uart";

			reg = <0xffc02100 0x100>;

			interrupts = <0 109 4>;

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

+1 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ 
};



&qspi {

	status = "okay";

	flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts

+4 −3
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ 
};



&qspi {

	status = "okay";

	flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;
@@ -211,12 +212,12 @@ 


			qspi_boot: partition@0 {

				label = "Boot and fpga data";

				reg = <0x0 0x034B0000>;

				reg = <0x0 0x03FE0000>;

			};



			qspi_rootfs: partition@4000000 {

			qspi_rootfs: partition@3FE0000 {

				label = "Root Filesystem - JFFS2";

				reg = <0x034B0000 0x0EB50000>;

				reg = <0x03FE0000 0x0C020000>;

			};

		};

	};

CRA Git | Maintained and supported by SUSTech CRA and CCSE