Commit 263ac390 authored by Zong Li's avatar Zong Li Committed by Stephen Boyd
Browse files

clk: sifive: Fix the wrong bit field shift 



The clk enable bit should be 31 instead of 24.

Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reported-by: default avatarPragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent efc91ae4

drivers/clk/sifive/sifive-prci.h

+2 −2
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 


/* DDRPLLCFG1 */

#define PRCI_DDRPLLCFG1_OFFSET		0x10

#define PRCI_DDRPLLCFG1_CKE_SHIFT	24

#define PRCI_DDRPLLCFG1_CKE_SHIFT	31

#define PRCI_DDRPLLCFG1_CKE_MASK	(0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)



/* GEMGXLPLLCFG0 */
@@ -81,7 +81,7 @@ 


/* GEMGXLPLLCFG1 */

#define PRCI_GEMGXLPLLCFG1_OFFSET	0x20

#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT	24

#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT	31

#define PRCI_GEMGXLPLLCFG1_CKE_MASK	(0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)



/* CORECLKSEL */

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