Commit 263225c9 authored by Srinivas Pandruvada's avatar Srinivas Pandruvada Committed by Andy Shevchenko
Browse files

tools/power/x86/intel-speed-select: Extend command set for perf-profile 



Add support for uncore P0, uncore P1, P1 for base and AVX levels and
memory frequency. These commands are optional, so continue on
failure.

Signed-off-by: default avatarSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
parent 3caa6f39

tools/power/x86/intel-speed-select/isst-core.c

+67 −0
Original line number Diff line number Diff line
@@ -95,6 +95,69 @@ int isst_get_pwr_info(int cpu, int config_index, 
	return 0;

}



void isst_get_uncore_p0_p1_info(int cpu, int config_index,

				struct isst_pkg_ctdp_level_info *ctdp_level)

{

	unsigned int resp;

	int ret;

	ret = isst_send_mbox_command(cpu, CONFIG_TDP,

				     CONFIG_TDP_GET_UNCORE_P0_P1_INFO, 0,

				     config_index, &resp);

	if (ret) {

		ctdp_level->uncore_p0 = 0;

		ctdp_level->uncore_p1 = 0;

		return;

	}



	ctdp_level->uncore_p0 = resp & GENMASK(7, 0);

	ctdp_level->uncore_p1 = (resp & GENMASK(15, 8)) >> 8;

	debug_printf(

		"cpu:%d ctdp:%d CONFIG_TDP_GET_UNCORE_P0_P1_INFO resp:%x uncore p0:%d uncore p1:%d\n",

		cpu, config_index, resp, ctdp_level->uncore_p0,

		ctdp_level->uncore_p1);

}



void isst_get_p1_info(int cpu, int config_index,

		      struct isst_pkg_ctdp_level_info *ctdp_level)

{

	unsigned int resp;

	int ret;

	ret = isst_send_mbox_command(cpu, CONFIG_TDP, CONFIG_TDP_GET_P1_INFO, 0,

				     config_index, &resp);

	if (ret) {

		ctdp_level->sse_p1 = 0;

		ctdp_level->avx2_p1 = 0;

		ctdp_level->avx512_p1 = 0;

		return;

	}



	ctdp_level->sse_p1 = resp & GENMASK(7, 0);

	ctdp_level->avx2_p1 = (resp & GENMASK(15, 8)) >> 8;

	ctdp_level->avx512_p1 = (resp & GENMASK(23, 16)) >> 16;

	debug_printf(

		"cpu:%d ctdp:%d CONFIG_TDP_GET_P1_INFO resp:%x sse_p1:%d avx2_p1:%d avx512_p1:%d\n",

		cpu, config_index, resp, ctdp_level->sse_p1,

		ctdp_level->avx2_p1, ctdp_level->avx512_p1);

}



void isst_get_uncore_mem_freq(int cpu, int config_index,

			      struct isst_pkg_ctdp_level_info *ctdp_level)

{

	unsigned int resp;

	int ret;

	ret = isst_send_mbox_command(cpu, CONFIG_TDP, CONFIG_TDP_GET_MEM_FREQ,

				     0, config_index, &resp);

	if (ret) {

		ctdp_level->mem_freq = 0;

		return;

	}



	ctdp_level->mem_freq = resp & GENMASK(7, 0);

	debug_printf(

		"cpu:%d ctdp:%d CONFIG_TDP_GET_MEM_FREQ resp:%x uncore mem_freq:%d\n",

		cpu, config_index, resp, ctdp_level->mem_freq);

}



int isst_get_tjmax_info(int cpu, int config_index,

			struct isst_pkg_ctdp_level_info *ctdp_level)

{
@@ -600,6 +663,10 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) 
		if (ret)

			return ret;



		isst_get_uncore_p0_p1_info(cpu, i, ctdp_level);

		isst_get_p1_info(cpu, i, ctdp_level);

		isst_get_uncore_mem_freq(cpu, i, ctdp_level);



		if (ctdp_level->pbf_support) {

			ret = isst_get_pbf_info(cpu, i, &ctdp_level->pbf_info);

			if (!ret)

tools/power/x86/intel-speed-select/isst-display.c

+38 −1
Original line number Diff line number Diff line
@@ -352,10 +352,47 @@ void isst_ctdp_display_information(int cpu, FILE *outf, int tdp_level, 
		format_and_print(outf, base_level + 4, header, value);



		snprintf(header, sizeof(header), "base-frequency(MHz)");

		if (!ctdp_level->sse_p1)

			ctdp_level->sse_p1 = ctdp_level->tdp_ratio;

		snprintf(value, sizeof(value), "%d",

			 ctdp_level->tdp_ratio * DISP_FREQ_MULTIPLIER);

			  ctdp_level->sse_p1 * DISP_FREQ_MULTIPLIER);

		format_and_print(outf, base_level + 4, header, value);



		if (ctdp_level->avx2_p1) {

			snprintf(header, sizeof(header), "base-frequency-avx2(MHz)");

			snprintf(value, sizeof(value), "%d",

				 ctdp_level->avx2_p1 * DISP_FREQ_MULTIPLIER);

			format_and_print(outf, base_level + 4, header, value);

		}



		if (ctdp_level->avx512_p1) {

			snprintf(header, sizeof(header), "base-frequency-avx512(MHz)");

			snprintf(value, sizeof(value), "%d",

				 ctdp_level->avx512_p1 * DISP_FREQ_MULTIPLIER);

			format_and_print(outf, base_level + 4, header, value);

		}



		if (ctdp_level->uncore_p1) {

			snprintf(header, sizeof(header), "uncore-frequency-min(MHz)");

			snprintf(value, sizeof(value), "%d",

				 ctdp_level->uncore_p1 * DISP_FREQ_MULTIPLIER);

			format_and_print(outf, base_level + 4, header, value);

		}



		if (ctdp_level->uncore_p0) {

			snprintf(header, sizeof(header), "uncore-frequency-max(MHz)");

			snprintf(value, sizeof(value), "%d",

				 ctdp_level->uncore_p0 * DISP_FREQ_MULTIPLIER);

			format_and_print(outf, base_level + 4, header, value);

		}



		if (ctdp_level->mem_freq) {

			snprintf(header, sizeof(header), "mem-frequency(MHz)");

			snprintf(value, sizeof(value), "%d",

				 ctdp_level->mem_freq * DISP_FREQ_MULTIPLIER);

			format_and_print(outf, base_level + 4, header, value);

		}



		snprintf(header, sizeof(header),

			 "speed-select-turbo-freq");

		if (ctdp_level->fact_support) {

CRA Git | Maintained and supported by SUSTech CRA and CCSE