drm/i915: PLL defines for VLV (25eb05fc) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_reg.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -796,7 +796,9 @@
		#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
		#define DPLL_VCO_ENABLE (1 << 31)
		#define DPLL_DVO_HIGH_SPEED (1 << 30)
		#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
		#define DPLL_SYNCLOCK_ENABLE (1 << 29)
		#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
		#define DPLL_VGA_MODE_DIS (1 << 28)
		#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
		#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
		@@ -808,6 +810,7 @@
		#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
		#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
		#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
		#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)

		#define SRX_INDEX 0x3c4
		#define SRX_DATA 0x3c5
		@@ -903,6 +906,7 @@
		#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
		#define _DPLL_B_MD 0x06020 /* 965+ only */
		#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)

		#define _FPA0 0x06040
		#define _FPA1 0x06044
		#define _FPB0 0x06048

+9 −1

Original line number	Diff line number	Diff line
		@@ -3487,6 +3487,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
		return true;
		}

		static int valleyview_get_display_clock_speed(struct drm_device *dev)
		{
		return 400000; /* FIXME */
		}

		static int i945_get_display_clock_speed(struct drm_device *dev)
		{
		return 400000;
		@@ -8987,7 +8992,10 @@ static void intel_init_display(struct drm_device *dev)
		}

		/* Returns the core display clock speed */
		if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		if (IS_VALLEYVIEW(dev))
		dev_priv->display.get_display_clock_speed =
		valleyview_get_display_clock_speed;
		else if (IS_I945G(dev) \|\| (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
		dev_priv->display.get_display_clock_speed =
		i945_get_display_clock_speed;
		else if (IS_I915G(dev))