Commit 25a49445 authored by Paul Zimmerman's avatar Paul Zimmerman Committed by Greg Kroah-Hartman
Browse files

staging: dwc2: remove use of bus_to_virt() 



Remove the use of bus_to_virt() and just fail the transfer if an
unaligned buffer with no virtual address is found. AFAIK that
can't happen anyway.

Also change setting of coherent DMA mask to the normal 32 bits.
31 bits was only needed when calling bus_to_virt() AFAICR.

Signed-off-by: default avatarPaul Zimmerman <paulz@synopsys.com>
Tested-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0cf31f86

drivers/staging/dwc2/Kconfig

+0 −1
Original line number Diff line number Diff line 
config USB_DWC2

	tristate "DesignWare USB2 DRD Core Support"

	depends on USB

	depends on VIRT_TO_BUS

	help

	  Say Y or M here if your system has a Dual Role HighSpeed

	  USB controller based on the DesignWare HSOTG IP Core.

drivers/staging/dwc2/hcd.c

+10 −10
Original line number Diff line number Diff line
@@ -2396,14 +2396,15 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 
						!(usb_pipein(urb->pipe))));



	buf = urb->transfer_buffer;



	if (hcd->self.uses_dma) {

		/*

		 * Calculate virtual address from physical address, because

		 * some class driver may not fill transfer_buffer.

		 * In Buffer DMA mode virtual address is used, when handling

		 * non-DWORD aligned buffers.

		 */

		buf = bus_to_virt(urb->transfer_dma);

		if (!buf && (urb->transfer_dma & 3)) {

			dev_err(hsotg->dev,

				"%s: unaligned transfer with no transfer_buffer",

				__func__);

			retval = -EINVAL;

			goto fail1;

		}

	}



	if (!(urb->transfer_flags & URB_NO_INTERRUPT))
@@ -2833,9 +2834,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 
	if (hsotg->core_params->dma_enable > 0) {

		if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)

			dev_warn(hsotg->dev, "can't set DMA mask\n");

		if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)

			dev_warn(hsotg->dev,

				 "can't enable workaround for >2GB RAM\n");

		if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)

			dev_warn(hsotg->dev, "can't set coherent DMA mask\n");

	} else {

		dma_set_mask(hsotg->dev, 0);

		dma_set_coherent_mask(hsotg->dev, 0);

CRA Git | Maintained and supported by SUSTech CRA and CCSE