Commit 259fef35 authored by Juston Li's avatar Juston Li Committed by Greg Kroah-Hartman
Browse files

staging: sm750fb: fix brace placement 



Fix brace placement errors caught by checkpatch.pl
ERROR: that open brace { should be on the previous line

Signed-off-by: default avatarJuston Li <juston.h.li@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a1fe154f

drivers/staging/sm750fb/ddk750_chip.h

+4 −8
Original line number Diff line number Diff line
@@ -8,8 +8,7 @@ 
#include <linux/io.h>



/* This is all the chips recognized by this library */

typedef enum _logical_chip_type_t

{

typedef enum _logical_chip_type_t {

	SM_UNKNOWN,

	SM718,

	SM750,
@@ -18,8 +17,7 @@ typedef enum _logical_chip_type_t 
logical_chip_type_t;





typedef enum _clock_type_t

{

typedef enum _clock_type_t {

	MXCLK_PLL,

	PRIMARY_PLL,

	SECONDARY_PLL,
@@ -28,8 +26,7 @@ typedef enum _clock_type_t 
}

clock_type_t;



typedef struct _pll_value_t

{

typedef struct _pll_value_t {

	clock_type_t clockType;

	unsigned long inputFreq; /* Input clock frequency to the PLL */
@@ -42,8 +39,7 @@ typedef struct _pll_value_t 
pll_value_t;



/* input struct to initChipParam() function */

typedef struct _initchip_param_t

{

typedef struct _initchip_param_t {

	unsigned short powerMode;    /* Use power mode 0 or 1 */

	unsigned short chipClock;    /**

				      * Speed of main chip clock in MHz unit

drivers/staging/sm750fb/ddk750_display.c

+18 −38
Original line number Diff line number Diff line
@@ -15,12 +15,10 @@ static void setDisplayControl(int ctrl, int dispState) 
	cnt = 0;



	/* Set the primary display control */

	if (!ctrl)

	{

	if (!ctrl) {

		ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);

		/* Turn on/off the Panel display control */

		if (dispState)

		{

		if (dispState) {

			/* Timing should be enabled first before enabling the plane

			 * because changing at the same time does not guarantee that

			 * the plane will also enabled or disabled.
@@ -45,16 +43,13 @@ static void setDisplayControl(int ctrl, int dispState) 
			 * until a few delay. Need to write

			 * and read it a couple times

			 */

			do

			{

			do {

				cnt++;

				POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);

			} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=

					(ulDisplayCtrlReg & ~ulReservedBits));

			printk("Set Panel Plane enbit:after tried %d times\n", cnt);

		}

		else

		{

		} else {

			/* When turning off, there is no rule on the programming

			 * sequence since whenever the clock is off, then it does not

			 * matter whether the plane is enabled or disabled.
@@ -71,14 +66,11 @@ static void setDisplayControl(int ctrl, int dispState) 
			POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);

		}



	}

	} else {

		/* Set the secondary display control */

	else

	{

		ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);



		if (dispState)

		{

		if (dispState) {

			/* Timing should be enabled first before enabling the plane because changing at the

			   same time does not guarantee that the plane will also enabled or disabled.

			   */
@@ -100,16 +92,13 @@ static void setDisplayControl(int ctrl, int dispState) 
				FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |

				FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);



			do

			{

			do {

				cnt++;

				POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);

			} while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=

					(ulDisplayCtrlReg & ~ulReservedBits));

				printk("Set Crt Plane enbit:after tried %d times\n", cnt);

		}

		else

		{

		} else {

			/* When turning off, there is no rule on the programming

			 * sequence since whenever the clock is off, then it does not

			 * matter whether the plane is enabled or disabled.
@@ -140,16 +129,13 @@ static void waitNextVerticalSync(int ctrl, int delay) 
		if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==

			 PANEL_PLL_CTRL_POWER_OFF) ||

			(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==

			 PANEL_DISPLAY_CTRL_TIMING_DISABLE))

		{

			 PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {

			return;

		}



		while (delay-- > 0)

		{

		while (delay-- > 0) {

			/* Wait for end of vsync. */

			do

			{

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

						   SYSTEM_CTRL,

						   PANEL_VSYNC);
@@ -157,8 +143,7 @@ static void waitNextVerticalSync(int ctrl, int delay) 
			while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);



			/* Wait for start of vsync. */

			do

			{

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

						   SYSTEM_CTRL,

						   PANEL_VSYNC);
@@ -173,16 +158,13 @@ static void waitNextVerticalSync(int ctrl, int delay) 
		if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) ==

			 CRT_PLL_CTRL_POWER_OFF) ||

			(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==

			 CRT_DISPLAY_CTRL_TIMING_DISABLE))

		{

			 CRT_DISPLAY_CTRL_TIMING_DISABLE)) {

			return;

		}



		while (delay-- > 0)

		{

		while (delay-- > 0) {

			/* Wait for end of vsync. */

			do

			{

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

								   SYSTEM_CTRL,

								   CRT_VSYNC);
@@ -190,8 +172,7 @@ static void waitNextVerticalSync(int ctrl, int delay) 
			while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);



			/* Wait for start of vsync. */

			do

			{

			do {

				status = FIELD_GET(PEEK32(SYSTEM_CTRL),

								   SYSTEM_CTRL,

								   CRT_VSYNC);
@@ -293,8 +274,7 @@ int ddk750_initDVIDisp(void) 
		     1,  /* Enable continuous Sync */

		     1,  /* Enable PLL Filter */

		     4   /* Use the recommended value for PLL Filter value */

		     ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000))

	{

		     ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000)) {

		return (-1);

	}

drivers/staging/sm750fb/ddk750_display.h

+1 −2
Original line number Diff line number Diff line
@@ -86,8 +86,7 @@ 
	CRT means crt path DSUB

*/

#if 0

typedef enum _disp_output_t

{

typedef enum _disp_output_t {

	NO_DISPLAY = DPMS_OFF,



	LCD1_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|DPMS_OFF|DAC_ON,

drivers/staging/sm750fb/ddk750_dvi.c

+2 −4
Original line number Diff line number Diff line
@@ -9,8 +9,7 @@ 
/* This global variable contains all the supported driver and its corresponding

   function API. Please set the function pointer to NULL whenever the function

   is not supported. */

static dvi_ctrl_device_t g_dcftSupportedDviController[] =

{

static dvi_ctrl_device_t g_dcftSupportedDviController[] = {

#ifdef DVI_CTRL_SII164

	{

		.pfnInit = sii164InitChip,
@@ -45,8 +44,7 @@ int dviInit( 
{

	dvi_ctrl_device_t *pCurrentDviCtrl;

	pCurrentDviCtrl = g_dcftSupportedDviController;

	if (pCurrentDviCtrl->pfnInit != NULL)

	{

	if (pCurrentDviCtrl->pfnInit != NULL) {

		return pCurrentDviCtrl->pfnInit(edgeSelect, busSelect, dualEdgeClkSelect, hsyncEnable,

						vsyncEnable, deskewEnable, deskewSetting, continuousSyncEnable,

						pllFilterEnable, pllFilterValue);

drivers/staging/sm750fb/ddk750_hwi2c.c

+2 −4
Original line number Diff line number Diff line
@@ -106,8 +106,7 @@ static unsigned int hwI2CWriteData( 
	 * Note:

	 *      Only 16 byte can be accessed per i2c start instruction.

	 */

	do

	{

	do {

		/* Reset I2C by writing 0 to I2C_RESET register to clear the previous status. */

		POKE32(I2C_RESET, 0);
@@ -173,8 +172,7 @@ static unsigned int hwI2CReadData( 
	 * Note:

	 *      Only 16 byte can be accessed per i2c start instruction.

	 */

	do

	{

	do {

		/* Reset I2C by writing 0 to I2C_RESET register to clear all the status. */

		POKE32(I2C_RESET, 0);

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