Commit 258ff0cf authored by Dmitry Bogdanov's avatar Dmitry Bogdanov Committed by David S. Miller
Browse files

net: atlantic: minimal A2 HW bindings required for fw_ops 



This patch adds the bare minimum of A2 HW bindings required to
get fw_ops working.

Signed-off-by: default avatarDmitry Bogdanov <dbogdanov@marvell.com>
Signed-off-by: default avatarMark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f6761961

drivers/net/ethernet/aquantia/atlantic/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ atlantic-objs := aq_main.o \ 
	hw_atl/hw_atl_utils.o \

	hw_atl/hw_atl_utils_fw2x.o \

	hw_atl/hw_atl_llh.o \

	hw_atl2/hw_atl2_llh.o \

	macsec/macsec_api.o



atlantic-$(CONFIG_MACSEC) += aq_macsec.o

drivers/net/ethernet/aquantia/atlantic/aq_hw.h

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Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ struct aq_hw_s { 
	struct hw_atl_utils_fw_rpc rpc;

	s64 ptp_clk_offset;

	u16 phy_id;

	void *priv;

};



struct aq_ring_s;

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c

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+56 −0
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// SPDX-License-Identifier: GPL-2.0-only

/* Atlantic Network Driver

 * Copyright (C) 2020 Marvell International Ltd.

 */



#include "hw_atl2_llh.h"

#include "hw_atl2_llh_internal.h"

#include "aq_hw_utils.h"



void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,

				int len)

{

	int j = 0;

	int i;



	for (i = offset; i < offset + len; i++, j++)

		data[j] = aq_hw_read_reg(aq_hw,

					 HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i));

}



void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data,

				  int len)

{

	int j = 0;

	int i;



	for (i = offset; i < offset + len; i++, j++)

		aq_hw_write_reg(aq_hw, HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i),

				data[j]);

}



void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data,

				 int len)

{

	int j = 0;

	int i;



	for (i = offset; i < offset + len; i++, j++)

		data[j] = aq_hw_read_reg(aq_hw,

					 HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(i));

}



void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR,

			    HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK,

			    HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT,

			    finish);

}



u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw)

{

	return aq_hw_read_reg_bit(aq_hw, HW_ATL2_MIF_MCP_FINISHED_READ_ADR,

				  HW_ATL2_MIF_MCP_FINISHED_READ_MSK,

				  HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT);

}

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Atlantic Network Driver

 * Copyright (C) 2020 Marvell International Ltd.

 */



#ifndef HW_ATL2_LLH_H

#define HW_ATL2_LLH_H



#include <linux/types.h>



struct aq_hw_s;



/* get data from firmware shared input buffer */

void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data,

				int len);



/* set data into firmware shared input buffer */

void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data,

				  int len);



/* get data from firmware shared output buffer */

void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data,

				 int len);



/* set host finished write shared buffer indication */

void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish);



/* get mcp finished read shared buffer indication */

u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw);



#endif /* HW_ATL2_LLH_H */

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Atlantic Network Driver

 * Copyright (C) 2020 Marvell International Ltd.

 */



#ifndef HW_ATL2_LLH_INTERNAL_H

#define HW_ATL2_LLH_INTERNAL_H



/* Register address for firmware shared input buffer */

#define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U)

/* Register address for firmware shared output buffer */

#define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) (0x00013000U + (dword) * 0x4U)



/* pif_host_finished_buf_wr_i Bitfield Definitions

 * Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i".

 * PORT="pif_host_finished_buf_wr_i"

 */

/* Register address for bitfield rpif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR 0x00000e00u

/* Bitmask for bitfield pif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK 0x00000001u

/* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN 0xFFFFFFFEu

/* Lower bit position of bitfield pif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT 0

/* Width of bitfield pif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH 1

/* Default value of bitfield pif_host_finished_buf_wr_i */

#define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT 0x0



/* pif_mcp_finished_buf_rd_i Bitfield Definitions

 * Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i".

 * PORT="pif_mcp_finished_buf_rd_i"

 */

/* Register address for bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_ADR 0x00000e04u

/* Bitmask for bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_MSK 0x00000001u

/* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN 0xFFFFFFFEu

/* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT 0

/* Width of bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH 1

/* Default value of bitfield pif_mcp_finished_buf_rd_i */

#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0



#endif /* HW_ATL2_LLH_INTERNAL_H */

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