Commit 25824ca3 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



A few fixes for 4.19:
- Fix a small memory leak
- SR-IOV reset fix
- Fix locking in MMU-notifier error path
- Updated SDMA golden settings to fix a PRT hang

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180912154735.2683-1-alexander.deucher@amd.com
parents db7f06d4 0165de98

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+16 −9
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 
{

	struct drm_gem_object *gobj;

	unsigned long size;

	int r;



	gobj = drm_gem_object_lookup(p->filp, data->handle);

	if (gobj == NULL)
@@ -50,20 +51,26 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 
	p->uf_entry.tv.shared = true;

	p->uf_entry.user_pages = NULL;



	size = amdgpu_bo_size(p->uf_entry.robj);

	if (size != PAGE_SIZE || (data->offset + 8) > size)

		return -EINVAL;



	*offset = data->offset;



	drm_gem_object_put_unlocked(gobj);



	size = amdgpu_bo_size(p->uf_entry.robj);

	if (size != PAGE_SIZE || (data->offset + 8) > size) {

		r = -EINVAL;

		goto error_unref;

	}



	if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {

		amdgpu_bo_unref(&p->uf_entry.robj);

		return -EINVAL;

		r = -EINVAL;

		goto error_unref;

	}



	*offset = data->offset;



	return 0;



error_unref:

	amdgpu_bo_unref(&p->uf_entry.robj);

	return r;

}



static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
@@ -1262,10 +1269,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
error_abort:

	dma_fence_put(&job->base.s_fence->finished);

	job->base.s_fence = NULL;

	amdgpu_mn_unlock(p->mn);



error_unlock:

	amdgpu_job_free(job);

	amdgpu_mn_unlock(p->mn);

	return r;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -2063,6 +2063,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) 
	static enum amd_ip_block_type ip_order[] = {

		AMD_IP_BLOCK_TYPE_GMC,

		AMD_IP_BLOCK_TYPE_COMMON,

		AMD_IP_BLOCK_TYPE_PSP,

		AMD_IP_BLOCK_TYPE_IH,

	};
@@ -2093,7 +2094,6 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) 


	static enum amd_ip_block_type ip_order[] = {

		AMD_IP_BLOCK_TYPE_SMC,

		AMD_IP_BLOCK_TYPE_PSP,

		AMD_IP_BLOCK_TYPE_DCE,

		AMD_IP_BLOCK_TYPE_GFX,

		AMD_IP_BLOCK_TYPE_SDMA,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+5 −2
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
@@ -81,7 +82,8 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)

};



static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
@@ -109,7 +111,8 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 
	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)

};



static const struct soc15_reg_golden golden_settings_sdma_4_2[] =

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