Commit 258249ec authored by Ryan Mallon's avatar Ryan Mallon
Browse files

ep93xx: Move PHYS_BASE defines to local SoC header file



The PHYS_BASE defines in arch/arm/mach-ep93xx/include/mach-ep93xx-regs.h are
only used in the SoC code. Move the defines to a local header file.

Signed-off-by: default avatarRyan Mallon <rmallon@gmail.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@iki.fi>
Acked-by: default avatarHartley Sweeten <hsweeten@visionengravers.com>
parent fde7d904
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@@ -20,6 +20,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "soc.h"

static struct ep93xx_eth_data __initdata adssphere_eth_data = {
	.phy_id		= 1,
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@@ -43,6 +43,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "soc.h"

static void __init edb93xx_register_flash(void)
{
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@@ -20,6 +20,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "soc.h"

static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
	.phy_id		= 1,
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@@ -5,40 +5,6 @@
#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H

/*
 * EP93xx Physical Memory Map:
 *
 * The ASDO pin is sampled at system reset to select a synchronous or
 * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
 * the synchronous boot mode is selected.  When ASDO is "0" (i.e
 * pulled-down) the asynchronous boot mode is selected.
 *
 * In synchronous boot mode nSDCE3 is decoded starting at physical address
 * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
 * decoded at 0xf0000000.
 *
 * There is known errata for the EP93xx dealing with External Memory
 * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
 * Guidelines" for more information.  This document can be found at:
 *
 *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
 */

#define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
#define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
#define EP93XX_CS1_PHYS_BASE		0x10000000
#define EP93XX_CS2_PHYS_BASE		0x20000000
#define EP93XX_CS3_PHYS_BASE		0x30000000
#define EP93XX_PCMCIA_PHYS_BASE		0x40000000
#define EP93XX_CS6_PHYS_BASE		0x60000000
#define EP93XX_CS7_PHYS_BASE		0x70000000
#define EP93XX_SDCE0_PHYS_BASE		0xc0000000
#define EP93XX_SDCE1_PHYS_BASE		0xd0000000
#define EP93XX_SDCE2_PHYS_BASE		0xe0000000
#define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
#define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */

/*
 * EP93xx linux memory map:
 *
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@@ -22,6 +22,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "soc.h"

/*************************************************************************
 * Micro9 NOR Flash
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