Commit 256c0960 authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
Browse files

kvm/arm: use PSR_AA32 definitions 



Some code cares about the SPSR_ELx format for exceptions taken from
AArch32 to inspect or manipulate the SPSR_ELx value, which is already in
the SPSR_ELx format, and not in the AArch32 PSR format.

To separate these from cases where we care about the AArch32 PSR format,
migrate these cases to use the PSR_AA32_* definitions rather than
COMPAT_PSR_*.

There should be no functional change as a result of this patch.

Note that arm64 KVM does not support a compat KVM API, and always uses
the SPSR_ELx format, even for AArch32 guests.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent d64567f6

arch/arm/include/asm/kvm_emulate.h

+7 −7
Original line number Diff line number Diff line
@@ -26,13 +26,13 @@ 
#include <asm/cputype.h>



/* arm64 compatibility macros */

#define COMPAT_PSR_MODE_ABT	ABT_MODE

#define COMPAT_PSR_MODE_UND	UND_MODE

#define COMPAT_PSR_T_BIT	PSR_T_BIT

#define COMPAT_PSR_I_BIT	PSR_I_BIT

#define COMPAT_PSR_A_BIT	PSR_A_BIT

#define COMPAT_PSR_E_BIT	PSR_E_BIT

#define COMPAT_PSR_IT_MASK	PSR_IT_MASK

#define PSR_AA32_MODE_ABT	ABT_MODE

#define PSR_AA32_MODE_UND	UND_MODE

#define PSR_AA32_T_BIT		PSR_T_BIT

#define PSR_AA32_I_BIT		PSR_I_BIT

#define PSR_AA32_A_BIT		PSR_A_BIT

#define PSR_AA32_E_BIT		PSR_E_BIT

#define PSR_AA32_IT_MASK	PSR_IT_MASK



unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);

arch/arm64/include/asm/kvm_emulate.h

+5 −5
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr) 


static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)

{

	*vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;

	*vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;

}



/*
@@ -190,8 +190,8 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 
	u32 mode;



	if (vcpu_mode_is_32bit(vcpu)) {

		mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;

		return mode > COMPAT_PSR_MODE_USR;

		mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;

		return mode > PSR_AA32_MODE_USR;

	}



	mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
@@ -329,7 +329,7 @@ static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) 
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)

{

	if (vcpu_mode_is_32bit(vcpu)) {

		*vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;

		*vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;

	} else {

		u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);

		sctlr |= (1 << 25);
@@ -340,7 +340,7 @@ static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) 
static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)

{

	if (vcpu_mode_is_32bit(vcpu))

		return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);

		return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);



	return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));

}

arch/arm64/kvm/guest.c

+7 −7
Original line number Diff line number Diff line
@@ -107,14 +107,14 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 
	}



	if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {

		u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK;

		u32 mode = (*(u32 *)valp) & PSR_AA32_MODE_MASK;

		switch (mode) {

		case COMPAT_PSR_MODE_USR:

		case COMPAT_PSR_MODE_FIQ:

		case COMPAT_PSR_MODE_IRQ:

		case COMPAT_PSR_MODE_SVC:

		case COMPAT_PSR_MODE_ABT:

		case COMPAT_PSR_MODE_UND:

		case PSR_AA32_MODE_USR:

		case PSR_AA32_MODE_FIQ:

		case PSR_AA32_MODE_IRQ:

		case PSR_AA32_MODE_SVC:

		case PSR_AA32_MODE_ABT:

		case PSR_AA32_MODE_UND:

		case PSR_MODE_EL0t:

		case PSR_MODE_EL1t:

		case PSR_MODE_EL1h:

arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
static bool __hyp_text __is_be(struct kvm_vcpu *vcpu)

{

	if (vcpu_mode_is_32bit(vcpu))

		return !!(read_sysreg_el2(spsr) & COMPAT_PSR_E_BIT);

		return !!(read_sysreg_el2(spsr) & PSR_AA32_E_BIT);



	return !!(read_sysreg(SCTLR_EL1) & SCTLR_ELx_EE);

}

arch/arm64/kvm/regmap.c

+11 −11
Original line number Diff line number Diff line
@@ -112,22 +112,22 @@ static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = { 
unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)

{

	unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs.regs;

	unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;

	unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;



	switch (mode) {

	case COMPAT_PSR_MODE_USR ... COMPAT_PSR_MODE_SVC:

	case PSR_AA32_MODE_USR ... PSR_AA32_MODE_SVC:

		mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */

		break;



	case COMPAT_PSR_MODE_ABT:

	case PSR_AA32_MODE_ABT:

		mode = 4;

		break;



	case COMPAT_PSR_MODE_UND:

	case PSR_AA32_MODE_UND:

		mode = 5;

		break;



	case COMPAT_PSR_MODE_SYS:

	case PSR_AA32_MODE_SYS:

		mode = 0;	/* SYS maps to USR */

		break;
@@ -143,13 +143,13 @@ unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num) 
 */

static int vcpu_spsr32_mode(const struct kvm_vcpu *vcpu)

{

	unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;

	unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;

	switch (mode) {

	case COMPAT_PSR_MODE_SVC: return KVM_SPSR_SVC;

	case COMPAT_PSR_MODE_ABT: return KVM_SPSR_ABT;

	case COMPAT_PSR_MODE_UND: return KVM_SPSR_UND;

	case COMPAT_PSR_MODE_IRQ: return KVM_SPSR_IRQ;

	case COMPAT_PSR_MODE_FIQ: return KVM_SPSR_FIQ;

	case PSR_AA32_MODE_SVC: return KVM_SPSR_SVC;

	case PSR_AA32_MODE_ABT: return KVM_SPSR_ABT;

	case PSR_AA32_MODE_UND: return KVM_SPSR_UND;

	case PSR_AA32_MODE_IRQ: return KVM_SPSR_IRQ;

	case PSR_AA32_MODE_FIQ: return KVM_SPSR_FIQ;

	default: BUG();

	}

}

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